R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683544
Date 12/13/2021
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Document Table of Contents
Document Table of Contents x
1. Design Example Description 2. Quick Start Guide 3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide Archives 4. Document Revision History for the R-tile Avalon® Streaming Intel FPGA IP for PCI Express Design Example User Guide
1. Design Example Description x
1.1. Credit Initialization Sequence
1.1. Credit Initialization Sequence x
1.1.1. Credit Value Initialization and Return 1.1.2. Credit Distribution
2. Quick Start Guide x
2.1. Directory Structure 2.2. Generating the Design Example 2.3. Simulating the Design Example 2.4. Root Port BFM 2.5. Compiling the Design Example 2.6. Running the Design Example
2.3. Simulating the Design Example x
2.3.1. Testbench
2.3.1. Testbench x
2.3.1.1. Testbench Modules 2.3.1.2. Test Driver Module 2.3.1.3. PIO Design Example
2.4. Root Port BFM x
2.4.1. BFM Memory Map 2.4.2. Configuration Space Bus and Device Numbering 2.4.3. Configuration of Root Port and Endpoint 2.4.4. Issuing Read and Write Transactions to the Application Layer 2.4.5. BFM Procedures and Functions
2.4.5. BFM Procedures and Functions x
2.4.5.1. ebfm_barwr Procedure 2.4.5.2. ebfm_barwr_imm Procedure 2.4.5.3. ebfm_barrd_wait Procedure 2.4.5.4. ebfm_barrd_nowt Procedure 2.4.5.5. ebfm_cfgwr_imm_wait Procedure 2.4.5.6. ebfm_cfgwr_imm_nowt Procedure 2.4.5.7. ebfm_cfgrd_wait Procedure 2.4.5.8. ebfm_cfgrd_nowt Procedure 2.4.5.9. BFM Configuration Procedures 2.4.5.10. BFM Shared Memory Access Procedures 2.4.5.11. BFM Log and Message Procedures 2.4.5.12. Verilog HDL Formatting Functions
2.4.5.9. BFM Configuration Procedures x
2.4.5.9.1. ebfm_cfg_rp_ep Procedure 2.4.5.9.2. ebfm_cfg_decode_bar Procedure
2.4.5.10. BFM Shared Memory Access Procedures x
2.4.5.10.1. Shared Memory Constants 2.4.5.10.2. shmem_write Task 2.4.5.10.3. shmem_read Function 2.4.5.10.4. shmem_display Verilog HDL Function 2.4.5.10.5. shmem_fill Procedure 2.4.5.10.6. shmem_chk_ok Function
2.4.5.11. BFM Log and Message Procedures x
2.4.5.11.1. ebfm_display Verilog HDL Function 2.4.5.11.2. ebfm_log_stop_sim Verilog HDL Function 2.4.5.11.3. ebfm_log_set_suppressed_msg_mask Task 2.4.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 2.4.5.11.5. ebfm_log_open Verilog HDL Function 2.4.5.11.6. ebfm_log_close Verilog HDL Function
2.4.5.12. Verilog HDL Formatting Functions x
2.4.5.12.1. himage1 2.4.5.12.2. himage2 2.4.5.12.3. himage4 2.4.5.12.4. himage8 2.4.5.12.5. himage16 2.4.5.12.6. dimage1 2.4.5.12.7. dimage2 2.4.5.12.8. dimage3 2.4.5.12.9. dimage4 2.4.5.12.10. dimage5 2.4.5.12.11. dimage6 2.4.5.12.12. dimage7
1. Design Example Description
2. Quick Start Guide
3. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide Archives
4. Document Revision History for the R-tile Avalon® Streaming Intel FPGA IP for PCI Express Design Example User Guide

2.3. Simulating the Design Example

The simulation setup involves the use of a Root Port Bus Functional Model (BFM) to exercise the R-tile Avalon® Streaming IP for PCIe (DUT) as shown in the following figure.

Figure 12. PIO Design Example Simulation Testbench

For a more detailed description of the testbench and the modules inside it, refer to Testbench. Also, for more details on the Root Port BFM specifically, refer to the Root Port BFM section.

The following flow diagram shows the steps to simulate the design example:

Figure 13. Procedure
Note: R-tile does not support parallel PIPE simulations.
Table 4.  Steps to Run Simulation
Simulator Working Directory Instructions
Siemens* EDA QuestaSim* <my_design>/pcie_ed_tb/pcie_ed_tb/sim/mentor
  1. Invoke vsim (by typing vsim, which brings up a console window where you can run the following commands).
  2. set TOP_LEVEL_NAME "pcie_ed_tb.pcie_ed_tb"
  3. Type "do msim_setup.tcl".
    Note: Alternatively, use "source msim_setup.tcl".
  4. ld_debug
  5. run -all
  6. A successful simulation will include the following message: "Simulation stopped due to successful completion!"
VCS* <my_design>/pcie_ed_tb/pcie_ed_tb/sim/synopsys/vcs
  1. Type sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final" USER_DEFINED_SIM_OPTIONS="" TOP_LEVEL_NAME="pcie_ed_tb" | tee simulation.log
    Note: The command above is a single-line command.
  2. A successful simulation will include the following message: "Simulation stopped due to successful completion!"
Note:
To run a simulation in interactive mode, use the following steps: (if you already generated a simv executable in non-interactive mode, delete the simv and simv.diadir)
  1. Open the vcs_setup.sh file and add a debug option to the VCS command: vcs -kdb -debug_access+all
  2. Compile the design example: sh vcs_setup.sh USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final" SKIP_SIM=1 TOP_LEVEL_NAME="pcie_ed_tb"
  3. Start the simulation in interactive mode: simv -gui &
VCS* MX <my_design>/pcie_ed_tb/pcie_ed_tb/sim/synopsys/vcsmx
  1. Type sh vcsmx_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final" USER_DEFINED_SIM_OPTIONS="" TOP_LEVEL_NAME="pcie_ed_tb.pcie_ed_tb" | tee simulation.log
    Note: The command above is a single-line command.
  2. A successful simulation will include the message "Simulation stopped due to successful completion!".
Note:
To run a simulation in interactive mode, use the following steps: (if you already generated a simv executable in non-interactive mode, delete the simv and simv.diadir)
  1. Compile the design example: sh vcsmx_setup.sh USER_DEFINED_COMPILE_OPTIONS="-kdb" USER_DEFINED_ELAB_OPTIONS="-debug_access+all" USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final" USER_DEFINED_SIM_OPTIONS="" SKIP_SIM=1 TOP_LEVEL_NAME="pcie_ed_tb.pcie_ed_tb"
  2. Start the simulation in interactive mode: simv -gui &

The following figure shows the link status information for a Gen5 x16 Endpoint simulation:

Figure 14. Link Status for a Gen5 x16 Endpoint Simulation

After a successful simulation, the simulation.log file will contain the "successful completion" message as shown in the following figure:

Figure 15. Successful Simulation Message

This testbench simulates up to a Gen5 x16 variant.

The simulation reports, "Simulation stopped due to successful completion" if no errors occur.

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