Visible to Intel only — GUID: mwh1391807508964
Ixiasoft
Visible to Intel only — GUID: mwh1391807508964
Ixiasoft
8. Strategies for Improving Memory Access Efficiency
An interconnect topology connects shared global, constant, and local memory systems to their underlying memory. Interconnect includes access arbitration to memory ports.
Memory accesses compete for shared memory resources (that is, global, local, and constant memories). If your OpenCL kernel performs a large number of memory accesses, the Intel® FPGA SDK for OpenCL™ Offline Compiler must generate complex arbitration logic to handle the memory access requests. The complex arbitration logic might cause a drop in the maximum operating frequency (fMAX), which degrades kernel performance.
The following sections discuss memory access optimizations in detail. In summary, minimizing global memory accesses is beneficial for the following reasons:
- Typically, increases in OpenCL kernel performance lead to increases in global memory bandwidth requirements.
- The maximum global memory bandwidth is much smaller than the maximum local memory bandwidth.
- The maximum computational bandwidth of the FPGA is much larger than the global memory bandwidth.
Attention: Use local, private or constant memory whenever possible to increase the memory bandwidth of the kernel.
- General Guidelines on Optimizing Memory Accesses
Optimizing the memory accesses in your OpenCL™ kernels can improve overall kernel performance. - Optimize Global Memory Accesses
The offline compiler interleaves global memory across each of the external memory banks. - Performing Kernel Computations Using Constant, Local or Private Memory
To optimize memory access efficiency, minimize the number for global memory accesses by performing your OpenCL™ kernel computations in constant, local, or private memory. - Improving Kernel Performance by Banking the Local Memory
Specifying the numbanks(N) and bankwidth(M) advanced kernel attributes allows you to configure the local memory banks for parallel memory accesses. - Optimizing Accesses to Local Memory by Controlling the Memory Replication Factor
To control the memory replication factor, use the max_replicates kernel attribute in your OpenCL™ kernel. - Minimizing the Memory Dependencies for Loop Pipelining
Intel® FPGA SDK for OpenCL™ Offline Compiler ensures that the memory accesses from the same thread respects the program order. When you compile an NDRange kernel, use barriers to synchronize memory accesses across threads in the same work-group. - Static Memory Coalescing
Static memory coalescing is an Intel® FPGA SDK for OpenCL™ Offline Compiler optimization step that attempts to reduce the number of times a kernel accesses non-private memory.