Intel® Stratix® 10 Hard Processor System Component Reference Manual

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ID 683516
Date 12/14/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction to the Intel® Stratix® 10 Hard Processor System Component 2. Configuring the Intel® Stratix® 10 Hard Processor System Component 3. Simulating the Intel® Stratix® 10 HPS Component
1. Introduction to the Intel® Stratix® 10 Hard Processor System Component x
1.1. Cortex*-A53 MPCore* Processor 1.2. CoreSight* Debug Components 1.3. Interconnect 1.4. FPGA Bridges 1.5. Memory Controllers 1.6. Support Peripherals 1.7. Introduction to the HPS Component Revision History
1.6. Support Peripherals x
1.6.1. Interface Peripherals 1.6.2. On-Chip Memories
2. Configuring the Intel® Stratix® 10 Hard Processor System Component x
2.1. Parameterizing the HPS Component 2.2. FPGA Interfaces 2.3. HPS Clocks and Resets 2.4. SDRAM 2.5. I/O Delays 2.6. Pin MUX and Peripherals 2.7. Generating and Compiling the HPS Component 2.8. Using the Address Span Extender Component 2.9. Configuring the HPS Component Revision History
2.2. FPGA Interfaces x
2.2.1. General Interfaces 2.2.2. HPS-FPGA AXI Bridges 2.2.3. HPS Boot Source 2.2.4. DMA Controller Interface 2.2.5. Interrupts
2.2.1. General Interfaces x
2.2.1.1. Enable MPU Standby and Event Interfaces 2.2.1.2. Enable General Purpose Signals 2.2.1.3. Enable Debug APB Interface 2.2.1.4. Enable System Trace Macrocell (STM) Hardware Events 2.2.1.5. Enable FPGA Cross Trigger Interface 2.2.1.6. Enable DDR ARM Trace Bus (ATB)
2.2.2. HPS-FPGA AXI Bridges x
2.2.2.1. FPGA-to-HPS Slave Interface 2.2.2.2. HPS to FPGA AXI-4 Master Interface 2.2.2.3. Lightweight HPS to FPGA Master Interface 2.2.2.4. FPGA-to-HPS SDRAM AXI* -4 Slave Interface
2.2.5. Interrupts x
2.2.5.1. FPGA-to-HPS 2.2.5.2. HPS-to-FPGA
2.3. HPS Clocks and Resets x
2.3.1. Input Clocks 2.3.2. Internal Clocks and Output Clocks 2.3.3. Resets
2.3.1. Input Clocks x
2.3.1.1. External Clock Source 2.3.1.2. FPGA-to-HPS Clocks Source 2.3.1.3. Peripheral FPGA Clocks
2.3.2. Internal Clocks and Output Clocks x
2.3.2.1. Main PLL Output Clocks – Desired Frequencies 2.3.2.2. HPS to FPGA User Clocks 2.3.2.3. HPS Peripheral Clocks – Desired Frequencies 2.3.2.4. Clock Sources 2.3.2.5. PLL Report
2.6. Pin MUX and Peripherals x
2.6.1. Auto-Place IP 2.6.2. Advanced
3. Simulating the Intel® Stratix® 10 HPS Component x
3.1. Simulation Flows 3.2. Clock and Reset Interfaces 3.3. FPGA-to-HPS AXI* Slave Interface 3.4. HPS-to-FPGA AXI* Master Interface 3.5. Lightweight HPS-to-FPGA AXI* Master Interface 3.6. HPS-to-FPGA MPU Event Interface 3.7. Interrupts Interface 3.8. HPS-to-FPGA Debug APB Interface 3.9. FPGA-to-HPS System Trace Macrocell Hardware Event Interface 3.10. HPS-to-FPGA Cross-Trigger Interface 3.11. HPS-to-FPGA Trace Port Interface 3.12. FPGA-to-HPS DMA Handshake Interface 3.13. General Purpose Input Interface 3.14. EMIF Conduit 3.15. Simulating the HPS Component Revision History
3.1. Simulation Flows x
3.1.1. Setting Up the HPS Component for Simulation 3.1.2. Generating the HPS Simulation Model in Platform Designer 3.1.3. Running the Simulations
3.1.1. Setting Up the HPS Component for Simulation x
3.1.1.1. HPS Conduit Interfaces Connecting to the FPGA
3.1.3. Running the Simulations x
3.1.3.1. Running HPS RTL Simulation 3.1.3.2. Running HPS Post-Fit Simulation
3.1.3.2. Running HPS Post-Fit Simulation x
3.1.3.2.1. Post-Fit Simulation Files 3.1.3.2.2. BFM API Hierarchy Format
3.2. Clock and Reset Interfaces x
3.2.1. Clock Interface 3.2.2. Reset Interface
1. Introduction to the Intel® Stratix® 10 Hard Processor System Component
2. Configuring the Intel® Stratix® 10 Hard Processor System Component
3. Simulating the Intel® Stratix® 10 HPS Component

3.1.3.2.1. Post-Fit Simulation Files

Post-fit simulation is the simulation of the netlist generated from the original RTL design after it has been mapped, synthesized, and fit. The netlist represents the actual hardware and its connections as they appear in the FPGA. Intel® Quartus® Prime generates the netlist and can generate a Standard Delay Format (.sdf) file with the timing information for all connections. The simulation can be functional only (without the timing information) where all wires and gates take zero time, or it can be a timing simulation where the time for all transitions is based on the SDF information.

Post-fit simulation can serve a number of different purposes:
  • Used to perform a dynamic verification of the timing of the design.
  • Used to verify the functional correctness of either the design, the compilation flow (in particular, the fitter), or both.

This table uses the following symbols:

  • <ACDS install> = Intel® Complete Design Suite installation path
  • <Avalon Verification IP> = <ACDS install> /ip/altera/sopc_builder_ip/verification
  • <AXI Verification IP> = <ACDS install> /ip/altera/mentor_vip_ae
  • <HPS Post‑fit Sim> = <ACDS install> /ip/altera/hps/postfitter_simulation
  • <Device Sim Lib> = <ACDS install> /quartus/eda/sim_lib
Table 14.  Post-Fit Simulation Files

Library

Directory

File

Intel® Verification IP Library

<Avalon Verification IP>/lib/

verbosity_pkg.sv

avalon_mm_pkg.sv

avalon_utilities_pkg.sv

Avalon Clock Source BFM

<Avalon Verification IP>/altera_avalon_clock_source/

altera_avalon_clock_source.sv

Avalon Reset Source BFM

<Avalon Verification IP>/altera_avalon_reset_source/

altera_avalon_reset_source.sv

Avalon MM Slave BFM

<Avalon Verification IP>/altera_avalon_mm_slave_bfm/

altera_avalon_mm_slave_bfm.sv

Avalon Interrupt Sink BFM

<Avalon Verification IP>/altera_avalon_interrupt_sink/

altera_avalon_interrupt_sink.sv

Mentor AXI Verification IP Library

<AXI Verification IP>/common/

questa_mvc_svapi.svh

Mentor AXI3 BFM

<AXI Verification IP>/axi3/axi3/bfm/

mgc_common_axi.sv

mgc_axi_master.sv

mgc_axi_slave.sv

HPS Post‑Fit Simulation Library

<HPS Post‑fit Sim>/

All the files in the directory

Device Simulation Library4

<Device Sim Lib>/

altera_primitives.v

220model.v

sgate.v

altera_mf.v

altera_lnsim.sv

twentynm_atoms.v

fourteennm_atoms.sv

mentor/twentynm_atoms_ncrypt.sv

mentor/fourteennm_atoms_ncrypt.sv

EDA Netlist Writer Generated Post‑Fit Simulation Model

<User project directory>/

*.vo

*.vho

(Mixed‑language simulator is needed for Verilog HDL and VHDL mixed design)

User testbench files

<User project directory>/

*.v

*.sv

*.vhd

(Mixed‑language simulator is needed for Verilog HDL and VHDL mixed design)

4 The device simulation library is not needed with Modelsim‑ Intel® .
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