Generic Flash Programmer User Guide: Intel® Quartus® Prime Standard Edition

Download PDF
ID 683491
Date 5/15/2019
Public
Document Table of Contents
Document Table of Contents x
1. Generic Flash Programmer User Guide Intel® Quartus® Prime Standard Edition
1. Generic Flash Programmer User Guide Intel® Quartus® Prime Standard Edition x
1.1. Supported Devices and Configuration Methods 1.2. Quad SPI Flash Byte-Addressing 1.3. Generic Flash Programmer Operation 1.4. Generic Flash Programmer Flow Templates (Convert Programming File) 1.5. Generic Flash Programmer Settings Reference 1.6. Generic Flash Programmer User Guide Revision History
1.3. Generic Flash Programmer Operation x
1.3.1. Generic Flash Programming (Convert Programming File Dialog Box) 1.3.2. Erasing Flash Memory Sectors
1.3.1. Generic Flash Programming (Convert Programming File Dialog Box) x
1.3.1.1. Step 1: Generate Primary Device Programming Files 1.3.1.2. Step 2: Generate Secondary Programming Files (Convert Programming Files) 1.3.1.3. Step 3: Program the Flash Memory Device
1.3.1.2. Step 2: Generate Secondary Programming Files (Convert Programming Files) x
1.3.1.2.1. Enabling Bitstream Compression or Encryption (Convert Programming File Dialog Box) 1.3.1.2.2. Defining a New Flash Memory Configuration Device 1.3.1.2.3. Modifying Programming Flows
1.4. Generic Flash Programmer Flow Templates (Convert Programming File) x
1.4.1. Initialization Flow Templates (Convert Programming File) 1.4.2. Program Flow Template (Convert Programming File) 1.4.3. Erase Flow Template (Convert Programming File) 1.4.4. Verify/Blank-Check/Examine Flow Template (Convert Programming File) 1.4.5. Termination Flow Template (Convert Programming File) 1.4.6. Programming Flow Action Properties
1.5. Generic Flash Programmer Settings Reference x
1.5.1. Convert Programming File Dialog Box 1.5.2. Device and Pin Options 1.5.3. Compression and Encryption Settings (Convert Programming File) 1.5.4. SOF Data Properties Dialog Box (Convert Programming File)
1. Generic Flash Programmer User Guide Intel® Quartus® Prime Standard Edition

1.2. Quad SPI Flash Byte-Addressing

Quad SPI flash devices typically support either 3-byte addressing, 4-byte addressing, or both for programming operations. You can only configure Intel® FPGAs with a flash memory device with byte addressing that is compatible with the Intel® FPGA that you plan to configure.

The following table specifies the byte-addressing compatibility of Intel® FPGAs for supported flash memory devices:

Table 2.   Intel® FPGA Required Flash Memory Byte Addressing
FPGA Devices Required Flash Memory Byte Addressing
Intel® Arria® 10 devices 4-byte addressing
Intel® Cyclone® 10 LP devices 3-byte addressing
Arria® V, Cyclone® V, Stratix® V series devices
  • 3-byte addressing (limited memory address access1)
  • 4-byte addressing
Cyclone® IV, Cyclone® II, Cyclone® III, Arria® GX, Arria® II, Stratix® II, Stratix® III, Stratix® IV, Stratix® IV devices 3-byte addressing

Adding Dummy Clock Cycles

Flash memory devices must read either a 24-bit (3-byte) address, or 32-bit (4-byte) address before the flash device can start receiving data to write to the flash memory, or before outputting the data after the flash memory device receives a read command. Therefore, you must specify (or select a flash memory template that specifies) an appropriate dummy clock cycle value for the flash memory device, as Defining a New Flash Memory Configuration Device describes.

Figure 2.  Reading Configuration Data from Flash (3-Byte and 4-Byte Addressing)
Related Information
1 Flash devices that exceed 128 megabits (Mb) density require 4-byte addressing to access the memory space higher than 128 Mb. For flash devices that do not support non-volatile, 4-byte addressing setting, the FPGA cannot read the configuration image that has a start address beyond 128Mb. For the remote system update application, the FPGA cannot store images beyond 128Mb.
Level Two Title