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1. Integer Arithmetic Intel® FPGA IP Cores
2. LPM_COUNTER (Counter) IP Core
3. LPM_DIVIDE Intel® FPGA IP Core References
4. LPM_MULT (Multiplier) IP Core
5. LPM_ADD_SUB (Adder/Subtractor)
6. LPM_COMPARE (Comparator)
7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core
8. Intel FPGA Multiply Adder IP Core
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core
11. ALTMULT_ADD (Multiply-Adder) IP Core
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core
13. ALTSQRT (Integer Square Root) IP Core
14. PARALLEL_ADD (Parallel Adder) IP Core
15. Integer Arithmetic Intel® FPGA IP Cores User Guide Document Archives
16. Document Revision History for Integer Arithmetic Intel® FPGA IP Cores User Guide
7.1. ALTECC Encoder Features
7.2. Verilog HDL Prototype (ALTECC_ENCODER)
7.3. Verilog HDL Prototype (ALTECC_DECODER)
7.4. VHDL Component Declaration (ALTECC_ENCODER)
7.5. VHDL Component Declaration (ALTECC_DECODER)
7.6. VHDL LIBRARY_USE Declaration
7.7. Encoder Ports
7.8. Decoder Ports
7.9. Encoder Parameters
7.10. Decoder Parameters
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12.6. VHDL Component Declaration
The VHDL component declaration is located in the VHDL Design File (.vhd) altera_mf_components.vhd in the < Quartus® Prime installation directory>\libraries\vhdl\altera_mf directory.
component altmult_complex generic ( intended_device_family:string := "unused"; implementation_style:string := "AUTO"; pipeline:natural := 4; representation_a:string := "SIGNED"; representation_b:string := "SIGNED"; width_a:natural; width_b:natural; width_result:natural; lpm_hint:string := "UNUSED"; lpm_type:string := "altmult_complex"); port( aclr:in std_logic := '0'; clock:in std_logic := '0'; complex:in std_logic := '1'; dataa_imag:in std_logic_vector(width_a-1 downto 0); dataa_real:in std_logic_vector(width_a-1 downto 0); datab_imag:in std_logic_vector(width_b-1 downto 0); datab_real:in std_logic_vector(width_b-1 downto 0); ena:in std_logic := '1'; result_imag:out std_logic_vector(width_result-1 downto 0); result_real:out std_logic_vector(width_result-1 downto 0)); end component;