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1. Integer Arithmetic Intel® FPGA IP Cores
2. LPM_COUNTER (Counter) IP Core
3. LPM_DIVIDE Intel® FPGA IP Core References
4. LPM_MULT (Multiplier) IP Core
5. LPM_ADD_SUB (Adder/Subtractor)
6. LPM_COMPARE (Comparator)
7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core
8. Intel FPGA Multiply Adder IP Core
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core
11. ALTMULT_ADD (Multiply-Adder) IP Core
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core
13. ALTSQRT (Integer Square Root) IP Core
14. PARALLEL_ADD (Parallel Adder) IP Core
15. Integer Arithmetic Intel® FPGA IP Cores User Guide Document Archives
16. Document Revision History for Integer Arithmetic Intel® FPGA IP Cores User Guide
7.1. ALTECC Encoder Features
7.2. Verilog HDL Prototype (ALTECC_ENCODER)
7.3. Verilog HDL Prototype (ALTECC_DECODER)
7.4. VHDL Component Declaration (ALTECC_ENCODER)
7.5. VHDL Component Declaration (ALTECC_DECODER)
7.6. VHDL LIBRARY_USE Declaration
7.7. Encoder Ports
7.8. Decoder Ports
7.9. Encoder Parameters
7.10. Decoder Parameters
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9.2. Verilog HDL Prototype
The following Verilog HDL prototype is located in the Verilog Design File (.v) altera_mf.v in the < Quartus® Prime installation directory>\eda\synthesis directory.
module altmemmult #( parameter coeff_representation = "SIGNED", parameter coefficient0 = "UNUSED", parameter data_representation = "SIGNED", parameter intended_device_family = "unused", parameter max_clock_cycles_per_result = 1, parameter number_of_coefficients = 1, parameter ram_block_type = "AUTO", parameter total_latency = 1, parameter width_c = 1, parameter width_d = 1, parameter width_r = 1, parameter width_s = 1, parameter lpm_type = "altmemmult", parameter lpm_hint = "unused") ( input wire clock, input wire [width_c-1:0]coeff_in, input wire [width_d-1:0] data_in, output wire load_done, output wire [width_r-1:0] result, output wire result_valid, input wire sclr, input wire [width_s-1:0] sel, input wire sload_coeff, input wire sload_data)/* synthesis syn_black_box=1 */; endmodule