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1. Integer Arithmetic Intel® FPGA IP Cores
2. LPM_COUNTER (Counter) IP Core
3. LPM_DIVIDE Intel® FPGA IP Core References
4. LPM_MULT (Multiplier) IP Core
5. LPM_ADD_SUB (Adder/Subtractor)
6. LPM_COMPARE (Comparator)
7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core
8. Intel FPGA Multiply Adder IP Core
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core
11. ALTMULT_ADD (Multiply-Adder) IP Core
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core
13. ALTSQRT (Integer Square Root) IP Core
14. PARALLEL_ADD (Parallel Adder) IP Core
15. Integer Arithmetic Intel® FPGA IP Cores User Guide Document Archives
16. Document Revision History for Integer Arithmetic Intel® FPGA IP Cores User Guide
7.1. ALTECC Encoder Features
7.2. Verilog HDL Prototype (ALTECC_ENCODER)
7.3. Verilog HDL Prototype (ALTECC_DECODER)
7.4. VHDL Component Declaration (ALTECC_ENCODER)
7.5. VHDL Component Declaration (ALTECC_DECODER)
7.6. VHDL LIBRARY_USE Declaration
7.7. Encoder Ports
7.8. Decoder Ports
7.9. Encoder Parameters
7.10. Decoder Parameters
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12.8. Signals
Signal | Required | Description |
---|---|---|
aclr | No | Asynchronous clear for the complex multiplier. When the aclr signal is asserted high, the function is asynchronously cleared. |
sclr | No | Synchronous clear for the complex multiplier. When the sclr signal is asserted high, the function is synchronously cleared. Only available for Stratix® 10, Arria® 10 and Cyclone® 10 GX devices. |
clock | Yes | Clock input to the ALTMULT_COMPLEX function. |
dataa_imag[] | Yes | Imaginary input value for the data A signal of the complex multiplier. The size of the input signal depends on the WIDTH_A parameter value. |
dataa_real[] | Yes | Real input value for the data A signal of the complex multiplier. The size of the input signal depends on the WIDTH_A parameter value. |
datab_imag[] | Yes | Imaginary input value for the data B signal of the complex multiplier. The size of the input signal depends on the WIDTH_B parameter value. |
datab_real[] | Yes | Real input value for the data B signal of the complex multiplier. The size of the input signal depends on the WIDTH_B parameter value. |
ena | No | Active high clock enable for the clock signal of the complex multiplier. |
complex | No | Optional input to enable dynamic switching between 36 × 36 normal model and 18 × 18 complex mode. This input is only available in Stratix V devices. In the GUI, this parameter is referred as Dynamic Complex Mode. |
Signal | Required | Description |
---|---|---|
result_imag | Yes | Imaginary output value of the multiplier. The size of the output signal depends on the WIDTH_RESULT parameter value. |
result_real | Yes | Real output value of the multiplier. The size of the output signal depends on the WIDTH_RESULT parameter value. |