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1. Integer Arithmetic Intel® FPGA IP Cores
2. LPM_COUNTER (Counter) IP Core
3. LPM_DIVIDE Intel® FPGA IP Core References
4. LPM_MULT (Multiplier) IP Core
5. LPM_ADD_SUB (Adder/Subtractor)
6. LPM_COMPARE (Comparator)
7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core
8. Intel FPGA Multiply Adder IP Core
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core
11. ALTMULT_ADD (Multiply-Adder) IP Core
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core
13. ALTSQRT (Integer Square Root) IP Core
14. PARALLEL_ADD (Parallel Adder) IP Core
15. Integer Arithmetic Intel® FPGA IP Cores User Guide Document Archives
16. Document Revision History for Integer Arithmetic Intel® FPGA IP Cores User Guide
7.1. ALTECC Encoder Features
7.2. Verilog HDL Prototype (ALTECC_ENCODER)
7.3. Verilog HDL Prototype (ALTECC_DECODER)
7.4. VHDL Component Declaration (ALTECC_ENCODER)
7.5. VHDL Component Declaration (ALTECC_DECODER)
7.6. VHDL LIBRARY_USE Declaration
7.7. Encoder Ports
7.8. Decoder Ports
7.9. Encoder Parameters
7.10. Decoder Parameters
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11.5. Ports
The following tables list the input and output ports for the ALTMULT_ADD IP core.
Port Name | Required | Description |
---|---|---|
dataa[] | Yes | Data input to the multiplier. Input port [NUMBER_OF_MULTIPLIERS * WIDTH_A - 1..0] wide. |
datab[] | Yes | Data input to the multiplier. Input port [NUMBER_OF_MULTIPLIERS * WIDTH_B - 1..0] wide. |
clock[] | No | Clock input port [0..3] to the corresponding register. This port can be used by any register in the IP core. |
aclr[] | No | Input port [0..3]. Asynchronous clear input to the corresponding register. |
ena[] | No | Input port [0..3]. Clock enable for the corresponding clock[] port. |
signa | No | Specifies the numerical representation of the dataa[] port. If the signa port is high, the multiplier treats the dataa[] port as a signed two's complement number. If the signa port is low, the multiplier treats the dataa[] port as an unsigned number. |
signb | No | Specifies the numerical representation of the datab[] port. If the signb port is high, the multiplier treats the datab[] port as a signed two's complement number. If the signb port is low, the multiplier treats the datab[] port as an unsigned number. |
Port Name | Required | Description |
---|---|---|
Ports Available in Stratix IV devices only | ||
output_round | No | Enables dynamically controlled output rounding. When OUTPUT_ROUNDING is set to VARIABLE, output_round enables the final adder stage of rounding. |
output_saturate | No | Enables dynamically controlled output saturation. When OUTPUT_SATURATION is set to VARIABLE, output_saturate enables the final adder stage of saturation. |
chainout_round | No | Enables dynamically controlled chainout stage rounding. When CHAINOUT_ROUNDING is set to VARIABLE, chainout_round enables the chainout stage of rounding. |
chainout_saturate | No | Enables dynamically controlled chainout stage saturation. When CHAINOUT_SATURATION is set to VARIABLE, chainout_saturate enables the chainout stage of saturation. |
zero_chainout | No | Dynamically specifies whether the chainout value is zero. |
zero_loopback | No | Dynamically specifies whether the loopback value is zero. |
accum_sload | No | Dynamically specifies whether the accumulator value is zero. |
chainin | No | Adder result input bus from the preceding stage. Input port [WIDTH_CHAININ - 1..0] wide. |
rotate | No | Specifies dynamically controlled port rotation in shift mode. |
shift_right | No | Specifies dynamically controlled port shift right or left in shift mode. Values are 0 and 1. A value of 0 specifies a shift to the left, a value of 1 specifies a shift to the right. |
Port Name | Required | Description |
---|---|---|
result[] | Yes | Multiplier output port. Output port [WIDTH_RESULT - 1..0] wide. |
overflow | No | Overflow flag. If output_saturation is enabled, overflow flag is set. |
scanouta[] | No | Output of scan chain A. Output port [WIDTH_A - 1..0] wide. Do not use scanina[] and scaninb[] simultaneously. |
scanoutb[] | No | Output of scan chain B. Output port [WIDTH_B - 1..0] wide. Do not use scanina[] and scaninb[] simultaneously. |
Port Name | Required | Description |
---|---|---|
chainout_sat_overflow | No | Overflow flag for the chainout saturation. |