Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions: User Guide

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ID 683488
Date 5/02/2016
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the SR-IOV DMA Example Design 3. Parameter Settings 4. Interfaces and Signal Descriptions 5. Registers 6. Programming and Testing SR-IOV Bridge MSI Interrupts 7. Error Handling 8. IP Core Architecture 9. Design Implementation 10. Transceiver PHY IP Reconfiguration 11. Debugging A. Frequently Asked Questions for PCI Express B. Transaction Layer Packet (TLP) Header Formats C. Stratix V Avalon-ST with SR-IOV Interface for PCIe Solutions User Guide Archive 12. Document Revision History
1. Datasheet x
1.1. Stratix® V Avalon-ST Interface with SR-IOV for PCIe Datasheet 1.2. Release Information 1.3. Device Family Support 1.4. Design Examples for SR-IOV 1.5. Debug Features 1.6. IP Core Verification 1.7. Performance and Resource Utilization 1.8. Recommended Speed Grades for SR-IOV Interface 1.9. Creating a Design for PCI Express
1.1. Stratix® V Avalon-ST Interface with SR-IOV for PCIe Datasheet x
1.1.1. SR-IOV Features
1.6. IP Core Verification x
1.6.1. Compatibility Testing Environment
2. Getting Started with the SR-IOV DMA Example Design x
2.1. Generating the Example Design Testbench 2.2. Understanding the Generated Files and Directories 2.3. Simulating the SR-IOV Example Design 2.4. Running a Gate-Level Simulation 2.5. Understanding the DMA Functionality 2.6. Compiling the Example Design with the Quartus® Prime Software 2.7. Using the IP Catalog To Generate Your Stratix V Hard IP for PCI Express as a Separate Component
3. Parameter Settings x
3.1. System Settings 3.2. SR-IOV System Settings 3.3. Base Address Register (BAR) Settings 3.4. SR-IOV Device Identification Registers 3.5. Interrupt Capabilities 3.6. PCI Express and PCI Capabilities Parameters 3.7. PHY Characteristics 3.8. Simulation Options
3.6. PCI Express and PCI Capabilities Parameters x
3.6.1. Device Capabilities 3.6.2. Error Reporting 3.6.3. Link Capabilities 3.6.4. Slot Capabilities 3.6.5. Power Management
4. Interfaces and Signal Descriptions x
4.1. Avalon-ST TX Interface 4.2. Component-Specific Avalon-ST Interface Signals 4.3. Avalon-ST RX Interface 4.4. BAR Hit Signals 4.5. Configuration Status Interface 4.6. Clock Signals 4.7. Function-Level Reset Interface 4.8. Interrupt Interface 4.9. Configuration Extension Bus (CEB) Interface 4.10. Implementing MSI-X Interrupts 4.11. Local Management Interface (LMI) Signals 4.12. Reset, Status, and Link Training Signals 4.13. Transceiver Reconfiguration 4.14. Serial Data Signals 4.15. Test Signals 4.16. PIPE Interface Signals
4.9. Configuration Extension Bus (CEB) Interface x
4.9.1. Vital Product Data (VPD) Capability
4.9.1. Vital Product Data (VPD) Capability x
4.9.1.1. Determine the Pointer Address of an External Capability Register 4.9.1.2. VPD Capability Implementation
4.14. Serial Data Signals x
4.14.1. Physical Layout of Hard IP In Stratix V Devices 4.14.2. Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. PCI and PCI Express Configuration Space Registers 5.3. MSI Registers 5.4. MSI-X Capability Structure 5.5. Power Management Capability Structure 5.6. PCI Express Capability Structure 5.7. Advanced Error Reporting (AER) Enhanced Capability Header Register 5.8. Uncorrectable Error Status Register 5.9. Uncorrectable Error Mask Register 5.10. Uncorrectable Error Severity Register 5.11. Correctable Error Status Register 5.12. Correctable Error Mask Register 5.13. Advanced Error Capabilities and Control Register 5.14. Header Log Registers 0-3 5.15. SR-IOV Virtualization Extended Capabilities Registers 5.16. Virtual Function Registers
5.2. PCI and PCI Express Configuration Space Registers x
5.2.1. Type 0 Configuration Space Registers 5.2.2. PCI and PCI Express Configuration Space Register Content 5.2.3. Interrupt Line and Interrupt Pin Register
5.15. SR-IOV Virtualization Extended Capabilities Registers x
5.15.1. SR-IOV Virtualization Extended Capabilities Registers Address Map 5.15.2. ARI Enhanced Capability Header 5.15.3. SR-IOV Enhanced Capability Registers 5.15.4. Initial VFs and Total VFs Registers 5.15.5. VF Device ID Register 5.15.6. Page Size Registers 5.15.7. VF Base Address Registers (BARs) 0-5 5.15.8. Secondary PCI Express Extended Capability Header 5.15.9. Lane Status Registers
6. Programming and Testing SR-IOV Bridge MSI Interrupts x
6.1. Setting Up and Verifying MSI Interrupts 6.2. Masking MSI Interrupts 6.3. Dropping a Pending MSI Interrupt
7. Error Handling x
7.1. Physical Layer Errors 7.2. Data Link Layer Errors 7.3. Transaction Layer Errors 7.4. Error Reporting and Data Poisoning 7.5. Uncorrectable and Correctable Error Status Bits
8. IP Core Architecture x
8.1. Data Link Layer 8.2. Physical Layer 8.3. Top-Level Interfaces 8.4. Physical and Virtual Function Address Assignments 8.5. Stratix V Hard IP for PCI Express with Single-Root I/O Virtualization (SR-IOV)
8.3. Top-Level Interfaces x
8.3.1. Avalon-ST Interface 8.3.2. Clocks and Reset 8.3.3. Transceiver Reconfiguration 8.3.4. Interrupts 8.3.5. PIPE
9. Design Implementation x
9.1. Making Analog QSF Assignments Using the Assignment Editor 9.2. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 9.3. Recommended Reset Sequence to Avoid Link Training Issues 9.4. SDC Timing Constraints
10. Transceiver PHY IP Reconfiguration x
10.1. Connecting the Transceiver Reconfiguration Controller IP Core 10.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
11. Debugging x
11.1. Setting Up Simulation 11.2. Hardware Bring-Up Issues 11.3. Link Training 11.4. Use Third-Party PCIe Analyzer 11.5. BIOS Enumeration Issues
11.1. Setting Up Simulation x
11.1.1. Changing Between Serial and PIPE Simulation 11.1.2. Using the PIPE Interface for Gen1 and Gen2 Variants 11.1.3. Viewing the Important PIPE Interface Signals 11.1.4. Disabling the Scrambler for Gen1 and Gen2 Simulations 11.1.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations 11.1.6. Changing between the Hard and Soft Reset Controller
11.3. Link Training x
11.3.1. Debugging Link that Fails To Reach L0
B. Transaction Layer Packet (TLP) Header Formats x
B.1. TLP Packet Formats without Data Payload B.2. TLP Packet Formats with Data Payload
12. Document Revision History x
12.1. Document Revision History for the Intel® Arria® 10 Avalon® Streaming with SR-IOV IP for PCIe* User Guide
1. Datasheet
2. Getting Started with the SR-IOV DMA Example Design
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Programming and Testing SR-IOV Bridge MSI Interrupts
7. Error Handling
8. IP Core Architecture
9. Design Implementation
10. Transceiver PHY IP Reconfiguration
11. Debugging
A. Frequently Asked Questions for PCI Express
B. Transaction Layer Packet (TLP) Header Formats
C. Stratix V Avalon-ST with SR-IOV Interface for PCIe Solutions User Guide Archive
12. Document Revision History

1.1.1. SR-IOV Features

Important changes in the Quartus® Prime 16.0 release:
  • Removed support for new designs using a 128-bit interface to the Application Layer.
  • Mature SR-IOV designs implemented in the 15.0 or 15.1 Quartus® Prime can continue to use the 128-bit interface. Refer to the archived 15.1 documentation, Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions Use Guide, 15.1 available on the Documentation Archive web page. Intel supports only the 256-bit interface to the Application Layer for new designs.
  • Changed the address map for many registers including, SR-IOV and Alternative Routing-ID (ARI) registers. Refer to SR-IOV Registers and Revision History chapters for more information.

The Stratix V Hard IP for PCI Express with SR-IOV supports the following features:

  • Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as hard IP.
  • Support for ×2, ×4, and ×8 configurations with Gen1, Gen2, or Gen3 lane rates for Endpoints. Downtrains to appropriate configuration when plugged into a lower bandwidth configuration, including Gen1 x1, Gen1 x2, and so on.
  • Dedicated 16 kilobyte (KB) receive buffer.
  • Optional hard reset controller for Gen2.
  • Qsys example designs demonstrating parameterization, design modules, and connectivity.
  • Extended credit allocation settings to better optimize the RX buffer space based on application type.
  • End-to-end cyclic redundancy code (ECRC) generation and checking and advanced error reporting (AER) for high reliability applications.
  • Support for Configuration Space Bypass Mode, allowing you to design a custom Configuration Space and support multiple functions.
  • Support for Gen3 PIPE simulation.
  • Easy to use:
    • Flexible configuration.
    • No license requirement.
    • Example designs to get started.
Table 2.  Feature Comparison for all Hard IP for PCI Express IP CoresThe table compares the features of the three mainstream Hard IP for PCI Express IP Cores. Refer to the Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions User Guide for the features of that variant.

Feature

Avalon-ST Interface

Avalon-MM Interface

Avalon-MM DMA

Avalon-ST with SR-IOV

IP Core License

Free

Free

Free

Free

Native Endpoint

Supported

Supported

Supported

Supported

Legacy Endpoint 1

Supported

Not Supported

Not Supported

Not supported

Root port

Supported

Supported

Not Supported

Not supported

Gen1

×1, ×2, ×4, ×8

×1, ×2, ×4, ×8

Not Supported

Not supported

Gen2

×1, ×2, ×4, ×8

×1, ×2, ×4, ×8

×4, ×8

×8

Gen3

×1, ×2, ×4, ×8

×1, ×2, ×4

×4, ×8

×4, ×8

64-bit Application Layer interface

Supported

Supported

Not supported

Not supported

128-bit Application Layer interface

Supported

Supported

Supported

Not supported

256‑bit Application Layer interface

Supported

Not Supported

Supported

Supported

Maximum payload size

128, 256, 512, 1024, 2048 bytes

128, 256 bytes

128, 256 bytes

 128, 256 bytes

Number of tags supported for non-posted requests

256

8

16

256

62.5 MHz clock

Supported

Supported

Not Supported

Not supported

Automatically handle out-of-order completions (transparent to the Application Layer)

Not supported

Supported

Not Supported

Not supported

Automatically handle requests that cross 4 KB address boundary (transparent to the Application Layer)

Not supported

Supported

Supported

Not supported

Polarity Inversion of PIPE interface signals

Supported

Supported

Supported

Supported

ECRC forwarding on RX and TX

Supported

Not supported

Not supported

Not supported

Number of MSI requests

1, 2, 4, 8, 16, or 32

1, 2, 4, 8, 16, or 32

1, 2, 4, 8, 16, or 32

1, 2, 4, 8, 16, or 32 (for Physical Functions)

MSI-X

Supported

Supported

Supported

Supported

Legacy interrupts

Supported

Supported

Supported

Supported

Expansion ROM

Supported

Not supported

Not supported

Not supported
PCIe bifurcation Not supported Not supported Not supported  
Table 3.  TLP Support Comparison for all Hard IP for PCI Express IP CoresThe table compares the TLP types that the four Hard IP for PCI Express IP Cores can transmit. Each entry indicates whether this TLP type is supported (for transmit) by endpoints (EP), Root Ports (RP), or both (EP/RP).

Transaction Layer Packet type (TLP) (transmit support)

Avalon-ST Interface

Avalon-MM Interface

Avalon-MM DMA

Avalon-ST with SR-IOV
Memory Read Request (Mrd) EP/RP EP/RP EP EP
Memory Read Lock Request (MRdLk) EP/RP   EP EP
Memory Write Request (MWr) EP/RP EP/RP EP EP
I/O Read Request (IORd) EP/RP EP/RP   EP
I/O Write Request (IOWr) EP/RP EP/RP   EP
Config Type 0 Read Request (CfgRd0) RP RP   EP
Config Type 0 Write Request (CfgWr0) RP RP   EP
Config Type 1 Read Request (CfgRd1) RP RP   EP
Config Type 1 Write Request (CfgWr1) RP RP   EP
Message Request (Msg) EP/RP EP/RP   EP
Message Request with Data (MsgD) EP/RP EP/RP   EP
Completion (Cpl) EP/RP EP/RP EP EP
Completion-Locked (CplLk) EP/RP     EP
Completion Lock with Data (CplDLk) EP/RP     EP
Fetch and Add AtomicOp Request (FetchAdd) EP      

The Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions User Guide explains how to use this IP core and not the PCI Express protocol. Although there is inevitable overlap between these two purposes, use this document only in conjunction with an understanding of the PCI Express Base Specification.

Note: This release provides separate user guides for the different variants. The Related Information provides links to all versions.
Related Information
1 Not recommended for new designs.
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