Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

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ID 683486
Date 4/09/2024
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Document Table of Contents
Document Table of Contents x
1. About the Low Latency E-Tile 40G Ethernet Intel® FPGA IP 2. Low Latency E-Tile 40G Ethernet IP Core Parameters 3. Getting Started 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide Archives 11. Comparison Between Low Latency E-Tile 40G Ethernet Core and Low Latency 40GbE IP Core 12. Document Revision History for Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide
1. About the Low Latency E-Tile 40G Ethernet Intel® FPGA IP x
1.1. Release Information 1.2. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Supported Features 1.3. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support 1.4. Resource Utilization
1.3. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support x
1.3.1. Device Family Support 1.3.2. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Device Speed Grade Support
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the Low Latency E-Tile 40G Ethernet IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Low Latency E-Tile 40G Ethernet IP Core Testbench 3.7. Compiling the Full Design and Programming the FPGA
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Ethernet Adaptation Flow 3.5.3. Placement Settings for the Low Latency E-Tile 40G Ethernet Core
3.6. Low Latency E-Tile 40G Ethernet IP Core Testbench x
3.6.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency E-Tile 40G Ethernet Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. Low Latency E-Tile 40G Ethernet Core Functional Description x
4.1.1. Low Latency E-Tile 40G Ethernet Core TX MAC Datapath 4.1.2. Low Latency E-Tile 40G Ethernet Core RX MAC Datapath 4.1.3. Link Fault Signaling Interface 4.1.4. Flow Control
4.1.1. Low Latency E-Tile 40G Ethernet Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC-32) Insertion
4.1.2. Low Latency E-Tile 40G Ethernet Core RX MAC Datapath x
4.1.2.1. IP Core Preamble Processing 4.1.2.2. IP Core Strict SFD Checking 4.1.2.3. Length/Type Field Processing 4.1.2.4. RX CRC Checking and Dynamic Forwarding
4.1.2.3. Length/Type Field Processing x
4.1.2.3.1. Length Checking
4.1.4. Flow Control x
4.1.4.1. TX Pause/PFC Flow Control Transmission 4.1.4.2. XON/XOFF Pause Frames
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers Signals 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers
9. Ethernet Toolkit Overview x
9.1. Features
1. About the Low Latency E-Tile 40G Ethernet Intel® FPGA IP
2. Low Latency E-Tile 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide Archives
11. Comparison Between Low Latency E-Tile 40G Ethernet Core and Low Latency 40GbE IP Core
12. Document Revision History for Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

6.1. TX MAC Interface to User Logic

The TX MAC provides an Avalon® streaming interface to the FPGA fabric. The datapath comprises 2, 64-bit words. The minimum packet size is nine bytes.
Table 13.   Avalon® Streaming TX MAC Interface SignalsAll interface signals are clocked by the clk_txmac clock. The value you specify for Ready latency in the Low Latency E-Tile 40G Ethernet parameter editor is the Avalon® streaming interface readyLatency value on this interface.

Signal

Direction

Description

clk_txmac Output

The TX clock for the IP core is clk_txmac. The frequency of this clock is 312.5  MHz.

If you turn on Use external TX MAC PLL in the Low Latency E-Tile 40G Ethernet parameter editor, the clk_txmac_in input clock drives clk_txmac.

l2_tx_data[127:0] Input

Data input to MAC. Bit 127 is the MSB and bit 0 is the LSB. Bytes are read in the usual left to right order.

l2_tx_preamble[63:0] Input

User preamble data. Available when you turn on Enable preamble passthrough in the Low Latency E-Tile 40G Ethernet parameter editor.

User logic drives the custom preamble data when l2_tx_startofpacket is asserted.
l2_tx_valid Input When asserted, indicates valid data.
l2_tx_startofpacket Input When asserted, indicates the first byte of a frame. When l2_tx_startofpacket is asserted, the MSB of l2_tx_data drives the start of packet. Packets that drive l2_tx_startofpacket and l2_tx_endofpacket in the same cycle are ignored.
l2_tx_endofpacket Input When asserted, indicates the end of a packet. Packets that drive l2_tx_startofpacket and l2_tx_endofpacket in the same cycle are ignored.
l2_tx_empty[3:0] Input Specifies the number of empty bytes when l2_tx_endofpacket is asserted.
l2_tx_ready Output When asserted, indicates that the MAC can accept the data. The IP core asserts the l2_tx_ready signal on clock cycle <n> to indicate that clock cycle <n + readyLatency> is a ready cycle. The client may only assert l2_tx_valid and transfer data during ready cycles.
l2_tx_error Input When asserted in an EOP cycle (while l2_tx_endofpacket is asserted), directs the IP core to insert an error in the packet before sending it on the Ethernet link.
Note: This functionality is not available in the Quartus Prime Pro 17.1 Stratix 10 ES Editions software.
l2_txstatus_valid Output When asserted, indicates that l2_txstatus_data and l2_txstatus_error[6:0] are driving valid data.
l2_txstatus_data[39:0] Output

Specifies information about the transmit frame. The following fields are defined:

  • [Bit 39]: When asserted, indicates a PFC frame
  • [Bit 38]: When asserted, indicates a unicast frame
  • Bit[37]: When asserted, indicates a multicast frame
  • Bit[36]: When asserted, indicates a broadcast frame
  • Bit[35]: When asserted, indicates a pause frame
  • Bit[34]: When asserted, indicates a control frame
  • Bit[33]: When asserted, indicates a VLAN frame
  • Bit[32]: When asserted, indicates a stacked VLAN frame
  • Bits[31:16]: Specifies the frame length from the first byte of the destination address to the last bye of the FCS
  • Bits[15:0]: Specifies the payload length
l2_txstatus_error[6:0] Output

Specifies the error type in the transmit frame. The following fields are defined:

  • Bits[6:3]: Reserved
  • Bit[2]: Payload length error
  • Bit[1]: Oversized frame
  • Bit[0]: Reserved.
Figure 12.  Client to MAC Avalon® streaming interface l2_tx_data reception order is highest byte to lowest byte. The first byte of the destination address is on l2_tx_data[127:120] , 0xabe4233 . . . in this timing diagram. The ready latency is 0 in this example.
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