Added 40GBASE-KR4 option with FEC and with auto-negotiation and link training mode options. |
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Added Synchronous Ethernet clock support option in Stratix V devices. The option separates the TX PLL and RX CDR input reference clocks (tx_ref_clk and rx_ref_clk signals replace ref_clk for these variations) and exposes the RX recovered clock. |
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Exposed link fault signals remote_fault_status and local_fault_status in duplex variations. |
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Exposed PHY status signals tx_lanes_stable and lanes_deskewed in MAC and PHY variations. |
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Updated and simplified the example design and testbench. The testbench stimulus is simpler and the user no longer needs to configure the DUT with a specific name and clock rate. |
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