Intel® Stratix® 10 TX Device Errata

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ID 683470
Date 7/21/2022
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Intel® -Specific Errata for the Intel® Stratix® 10 TX Devices 3. Arm* Cortex*-A53 MPCore* and CoreSight* Errata 4. Document Revision History for Intel® Stratix® 10 TX Device Errata
2. Intel® -Specific Errata for the Intel® Stratix® 10 TX Devices x
2.1. FPGA 2.2. Device Power Supply, Core and I/O 2.3. Hard Processor System
2.2. Device Power Supply, Core and I/O x
2.2.1. M20K Simple Quad-Port Mode Support
2.3. Hard Processor System x
2.3.1. HPS Stops on the First Read Request to SDRAM 2.3.2. Write Data Can Appear at an AXI Interface before the Write Address, which can Cause a Deadlock Condition
3. Arm* Cortex*-A53 MPCore* and CoreSight* Errata x
3.1. 843819: Memory Locations May be Accessed Speculatively Due to Instruction Fetches When HCR.VM is Set 3.2. 845719: A Load May Read Incorrect Data 3.3. 855871: ETM Does Not Report IDLE State When Disabled Using OSLOCK 3.4. 855872: A Store-Exclusive Instruction May Pass When it Should Fail 3.5. 711668: Configuration Extension Register Has Wrong Value Status 3.6. 720107: Periodic Synchronization Can Be Delayed and Cause Overflow 3.7. 855873: An Eviction Might Overtake a Cache Clean Operation 3.8. 853172: ETM May Assert AFREADY Before All Data Has Been Output 3.9. 836870: Non-Allocating Reads May Prevent a Store Exclusive From Passing 3.10. 836919: Write of the JMCR in EL0 Does Not Generate an UNDEFINED Exception 3.11. 845819: Instruction Sequences Containing AES Instructions May Produce Incorrect Results 3.12. 851672: ETM May Trace an Incorrect Exception Address 3.13. 851871: ETM May Lose Counter Events While Entering WFx Mode 3.14. 852071: Direct Branch Instructions Executed Before a Trace Flush May be Output in an Atom Packet After Flush Acknowledgment 3.15. 852521: A64 Unconditional Branch May Jump to Incorrect Address 3.16. 855827: PMU Counter Values May Be Inaccurate When Monitoring Certain Events 3.17. 855829: Reads of PMEVCNTR<n> are not Masked by HDCR.HPMN 3.18. 855830: Loads of Mismatched Size May not be Single-Copy Atomic
1. About this Document
2. Intel® -Specific Errata for the Intel® Stratix® 10 TX Devices
3. Arm* Cortex*-A53 MPCore* and CoreSight* Errata
4. Document Revision History for Intel® Stratix® 10 TX Device Errata

3.1. 843819: Memory Locations May be Accessed Speculatively Due to Instruction Fetches When HCR.VM is Set

Description

The Arm* v8 architecture requires that when all associated stages of translation are disabled for the current exception level, software only perform instruction fetches within the same or next translation granule as an instruction which has been or can be fetched due to sequential execution. In the conditions detailed below, this erratum may cause the Cortex-A53 MPCore* processor to access other locations speculatively due to instruction fetches.

For this erratum to occur:
  • The CPU must be executing at EL3, EL2 or Secure EL1.
  • The CPU can be in either AArch32 or AArch64 execution state.
  • Address translation is disabled for the current exception level (by clearing the appropriate SCTLR.M, HSCTLR.M or SCTLR_ELx.M bit).
  • The HCR.VM or HCR_EL2.VM bit is set.

Impact

If the above conditions are met, then speculative instruction fetches may be made to memory locations not permitted by the architecture.

Workaround

Because the HCR.VM bit default reset value is low, this situation is most likely to occur in power down code, if EL2 or EL3 software disables address translation before the core is powered down. To work around this erratum, software must clear the HCR.VM bit before disabling address translation at EL3, EL2 or Secure EL1.

Category

Category 2
Level Two Title