Intel® Quartus® Prime Pro Edition User Guide: Getting Started

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ID 683463
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Introduction to Intel® Quartus® Prime Pro Edition 2. Managing Intel® Quartus® Prime Projects 3. Design Planning 4. Introduction to Intel® FPGA IP Cores 5. Migrating to Intel® Quartus® Prime Pro Edition A. Intel® Quartus® Prime Pro Edition User Guides 6. Document Archives
1. Introduction to Intel® Quartus® Prime Pro Edition x
1.1. Selecting an Intel® Quartus® Prime Software Edition 1.2. Introduction to Intel® Quartus® Prime Pro Edition Revision History
2. Managing Intel® Quartus® Prime Projects x
2.1. Viewing Basic Project Information 2.2. Intel® Quartus® Prime Project Contents 2.3. Managing Project Settings 2.4. Managing Logic Design Files 2.5. Managing Timing Constraints 2.6. Integrating Other EDA Tools 2.7. Exporting Compilation Results 2.8. Migrating Projects Across Operating Systems 2.9. Archiving Projects 2.10. Command-Line Interface 2.11. Managing Projects Revision History
2.1. Viewing Basic Project Information x
2.1.1. Using the Compilation Dashboard 2.1.2. Viewing Project Reports 2.1.3. Viewing Project Messages 2.1.4. Automated Problem Reports
2.1.3. Viewing Project Messages x
2.1.3.1. Suppressing Message Display 2.1.3.2. Promoting Critical Warnings to Errors
2.2. Intel® Quartus® Prime Project Contents x
2.2.1. Project File Best Practices
2.3. Managing Project Settings x
2.3.1. Specifying the Target Device or Board 2.3.2. Optimizing Project Settings
2.3.2. Optimizing Project Settings x
2.3.2.1. Optimize Settings with Design Space Explorer II 2.3.2.2. Optimize Settings with Project Revisions 2.3.2.3. Back-Annotate Optimized Assignments
2.4. Managing Logic Design Files x
2.4.1. Including Design Libraries 2.4.2. Creating a Project Copy
2.7. Exporting Compilation Results x
2.7.1. Exporting a Version-Compatible Compilation Database 2.7.2. Importing a Version-Compatible Compilation Database 2.7.3. Creating a Design Partition 2.7.4. Exporting a Design Partition 2.7.5. Reusing a Design Partition 2.7.6. Viewing Quartus Database File Information 2.7.7. Clearing Compilation Results
2.7.6. Viewing Quartus Database File Information x
2.7.6.1. QDB File Attribute Types
2.8. Migrating Projects Across Operating Systems x
2.8.1. Migrating Design Files and Libraries 2.8.2. Design Library Migration Guidelines
2.8.1. Migrating Design Files and Libraries x
2.8.1.1. Use Relative Paths
2.9. Archiving Projects x
2.9.1. Manually Adding Files To Archives 2.9.2. Archiving Projects for Service Requests 2.9.3. Archiving Projects for External Revision Control 2.9.4. Creating Database-Only Archives
2.9.3. Archiving Projects for External Revision Control x
2.9.3.1. Project Files to Include In External Revision Control
2.10. Command-Line Interface x
2.10.1. Project Revision Commands 2.10.2. Project Archive Commands 2.10.3. Project Database Commands
2.10.3. Project Database Commands x
2.10.3.1. quartus_cdb Executables to Manage Version-Compatible Databases
3. Design Planning x
3.1. Design Planning 3.2. Create a Design Specification and Test Plan 3.3. Plan for the Target Device 3.4. Plan for Intellectual Property Cores 3.5. Plan for Standard Interfaces 3.6. Plan for Device Programming 3.7. Plan for Device Power Consumption 3.8. Plan for Interface I/O Pins 3.9. Plan for other EDA Tools 3.10. Plan for On-Chip Debugging Tools 3.11. Plan HDL Coding Styles 3.12. Plan for Hierarchical and Team-Based Designs 3.13. Design Planning Revision History
3.3. Plan for the Target Device x
Device Family Selection Guidelines 3.3.1. Device Migration Planning
3.8. Plan for Interface I/O Pins x
3.8.1. Simultaneous Switching Noise Analysis
3.9. Plan for other EDA Tools x
3.9.1. Third-Party Synthesis Tools 3.9.2. Third-Party Simulation Tools
3.11. Plan HDL Coding Styles x
3.11.1. Design Recommendations 3.11.2. Recommended HDL Coding Styles 3.11.3. Managing Metastability
3.12. Plan for Hierarchical and Team-Based Designs x
3.12.1. Flat Compilation without Design Partitions
4. Introduction to Intel® FPGA IP Cores x
4.1. IP Catalog and Parameter Editor 4.2. Installing and Licensing Intel® FPGA IP Cores 4.3. IP General Settings 4.4. Adding IP to IP Catalog 4.5. Best Practices for Intel® FPGA IP 4.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 4.7. Modifying an IP Variation 4.8. Upgrading IP Cores 4.9. Simulating Intel® FPGA IP Cores 4.10. Simulating Platform Designer Systems 4.11. Synthesizing IP Cores in Other EDA Tools 4.12. Instantiating IP Cores in HDL 4.13. Support for the IEEE 1735 Encryption Standard 4.14. Introduction to Intel FPGA IP Cores Revision History
4.1. IP Catalog and Parameter Editor x
4.1.1. The Parameter Editor
4.2. Installing and Licensing Intel® FPGA IP Cores x
4.2.1. Intel® FPGA IP Evaluation Mode
4.2.1. Intel® FPGA IP Evaluation Mode x
4.2.1.1. Intel FPGA IP Versioning 4.2.1.2. Checking the IP License Status
4.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
4.6.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 4.6.2. Scripting IP Core Generation
4.8. Upgrading IP Cores x
4.8.1. Upgrading IP Cores at Command-Line 4.8.2. Migrating IP Cores to a Different Device 4.8.3. Troubleshooting IP or Platform Designer System Upgrade
4.9. Simulating Intel® FPGA IP Cores x
4.9.1. Generating IP Simulation Files 4.9.2. Scripting IP Simulation
4.9.2. Scripting IP Simulation x
4.9.2.1. Generating a Combined Simulator Setup Script ( Intel® Quartus® Prime Pro Edition)
4.12. Instantiating IP Cores in HDL x
4.12.1. Example Top-Level Verilog HDL Module 4.12.2. Example Top-Level VHDL Module
5. Migrating to Intel® Quartus® Prime Pro Edition x
5.1. Keep Pro Edition Project Files Separate 5.2. Upgrade Project Assignments and Constraints 5.3. Upgrade IP Cores and Platform Designer Systems 5.4. Upgrade Non-Compliant Design RTL 5.5. Migrating to Intel® Quartus® Prime Pro Edition Revision History
5.2. Upgrade Project Assignments and Constraints x
5.2.1. Modify Entity Name Assignments 5.2.2. Resolve Timing Constraint Entity Names 5.2.3. Verify Generated Node Name Assignments 5.2.4. Replace Logic Lock (Standard) Regions 5.2.5. Modify Signal Tap Logic Analyzer Files 5.2.6. Remove References to .qip Files 5.2.7. Remove Unsupported Feature Assignments
5.2.4. Replace Logic Lock (Standard) Regions x
5.2.4.1. Logic Lock Region Assignment Examples
5.4. Upgrade Non-Compliant Design RTL x
5.4.1. Verify Verilog Compilation Unit 5.4.2. Update Entity Auto-Discovery 5.4.3. Ensure Distinct VHDL Namespace for Each Library 5.4.4. Remove Unsupported Parameter Passing 5.4.5. Remove Unsized Constant from WYSIWYG Instantiation 5.4.6. Remove Non-Standard Pragmas 5.4.7. Declare Objects Before Initial Values 5.4.8. Confine SystemVerilog Features to SystemVerilog Files 5.4.9. Avoid Assignment Mixing in Always Blocks 5.4.10. Avoid Unconnected, Non-Existent Ports 5.4.11. Avoid Illegal Parameter Ranges 5.4.12. Update Verilog HDL and VHDL Type Mapping
5.4.1. Verify Verilog Compilation Unit x
5.4.1.1. Verilog HDL Configuration Instantiation
1. Introduction to Intel® Quartus® Prime Pro Edition
2. Managing Intel® Quartus® Prime Projects
3. Design Planning
4. Introduction to Intel® FPGA IP Cores
5. Migrating to Intel® Quartus® Prime Pro Edition
A. Intel® Quartus® Prime Pro Edition User Guides
6. Document Archives

3.3. Plan for the Target Device

Intel offers a broad portfolio of FPGA and PLD devices. The Intel® device that you select determines factors of performance, density, and board layout. To avoid costly design changes, it is best to carefully consider and determine the target device family early in the design cycle. Intel® FPGA device families differ in cost, size, density, performance, power consumption, packaging, I/O standards, and other factors. Select the device family that best suits your most critical design requirements.

Device Family Selection Guidelines

  • Refer to the Product Selector tool on the Intel® website to quickly find and compare the specifications and features of Intel® FPGA devices and development kits.
  • Once you identify the target device family, refer to the device family technical documentation for detailed device characteristics. Each device family includes complete documentation, including a datasheet and user guide or handbook. You can also view a summary of each device's resources by selecting a device in the Device dialog box (Assignments > Device)
    Figure 33. Device Dialog Box
  • Consider whether the device family meets any requirements you have for high-speed transceivers, global or regional clock networks, and the number of phase-locked loops (PLLs)
  • Consider the density requirements of your design. Devices with more logic resources and higher I/O counts can implement larger and more complex designs, but at a higher cost. Smaller devices use lower static power. Select a device larger than what your design requires if you may want to add more logic later in the design cycle, or to reserve logic and memory for on-chip debugging.
  • Consider requirements for types of dedicated logic blocks, such as memory blocks of different sizes, or digital signal processing (DSP) blocks to implement certain arithmetic functions.
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