Intel® High Level Synthesis Compiler Pro Edition: User Guide

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ID 683456
Date 6/20/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® High Level Synthesis Compiler Pro Edition User Guide 2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition 3. Creating a High-Level Synthesis Component and Testbench 4. Verifying the Functionality of Your Design 5. Optimizing and Refining Your Component 6. Verifying Your IP with Simulation 7. Synthesize your Component IP with Intel® Quartus® Prime Pro Edition 8. Integrating your IP into a System A. Reviewing the High-Level Design Reports (report.html) B. Intel® HLS Compiler Pro Edition Restrictions C. Intel® HLS Compiler Pro Edition User Guide Archives D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition x
2.1. High Level Synthesis Design Flow 2.2. The Project Directory
3. Creating a High-Level Synthesis Component and Testbench x
3.1. Intel® HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros
5. Optimizing and Refining Your Component x
5.1. The High-Level Design Reports
6. Verifying Your IP with Simulation x
6.1. Generation of the Verification Testbench Executable 6.2. Debugging during Verification 6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls
6.3. High-Throughput Simulation (Asynchronous Component Calls) Using Enqueue Function Calls x
6.3.1. Execution Model 6.3.2. Comparison of Explicit and Enqueued Function Calls
8. Integrating your IP into a System x
8.1. Adding the HLS Compiler-Generated IP into an Intel® Quartus® Prime Pro Edition Project 8.2. Adding the HLS Compiler-Generated IP into a Platform Designer System
A. Reviewing the High-Level Design Reports (report.html) x
A.1. Reviewing the Summary Report A.2. Reviewing Component Architecture A.3. Reviewing Factors That Affect Throughput A.4. Reviewing Component Area Usage A.5. Accessing HLD FPGA Reports in JSON Format
A.2. Reviewing Component Architecture x
A.2.1. System Viewer A.2.2. Function Memory Viewer A.2.3. Schedule Viewer (Beta)
A.2.1. System Viewer x
A.2.1.1. Reviewing System Information A.2.1.2. Reviewing Function Information A.2.1.3. Reviewing Block Information A.2.1.4. Reviewing Cluster Information
A.2.1.2. Reviewing Function Information x
A.2.1.2.1. Reviewing Component Interfaces A.2.1.2.2. Reviewing Loops and Blocks in Your Component or Task
A.3. Reviewing Factors That Affect Throughput x
A.3.1. Loop Analysis Report A.3.2. Loops Viewer (Alpha) A.3.3. Verification Statistics Report
1. Intel® High Level Synthesis Compiler Pro Edition User Guide
2. Overview of the Intel® High Level Synthesis (HLS) Compiler Pro Edition
3. Creating a High-Level Synthesis Component and Testbench
4. Verifying the Functionality of Your Design
5. Optimizing and Refining Your Component
6. Verifying Your IP with Simulation
7. Synthesize your Component IP with Intel® Quartus® Prime Pro Edition
8. Integrating your IP into a System
A. Reviewing the High-Level Design Reports (report.html)
B. Intel® HLS Compiler Pro Edition Restrictions
C. Intel® HLS Compiler Pro Edition User Guide Archives
D. Document Revision History for Intel® HLS Compiler Pro Edition User Guide

A.2.1.2.2. Reviewing Loops and Blocks in Your Component or Task

The Function Views of the System Viewer in the High Level Design Report (report.html) shows an abstracted netlist of your component design. In the Function Views, you can visualize loops in your component and your component interactions with its internal RAM block and external interfaces.

Consider the following code excerpt from the transpose_and_fold component (part of the tutorial files provided in <quartus_installdir>/hls/examples/tutorials/best_practices/loop_memory_dependency): 
#include "HLS/hls.h"
#include <stdio.h>
#include <stdlib.h>

#define SIZE 4

typedef ihc::stream_in<int> my_operand;
typedef ihc::stream_out<int> my_result;

component void transpose_and_fold(my_operand &data_in, my_result &res)
{
  int i;
  int j;
  int in_buf[SIZE][SIZE] hls_memory;
  int tmp_buf[SIZE][SIZE] hls_memory;
  for (i = 0; i < SIZE * SIZE; i++) {
    in_buf[i / SIZE][i % SIZE] = data_in.read();
    tmp_buf[i / SIZE][i % SIZE] = 0;
  }

  #ifdef USE_IVDEP
  #pragma ivdep safelen(SIZE)
  #endif
  for (j = 0; j < SIZE * SIZE * SIZE; j++) {
  #pragma unroll
    for (i = 0; i < SIZE; i++) {
      tmp_buf[j % SIZE][i] += in_buf[i][j % SIZE];
    }
  }
  for (i = 0; i < SIZE * SIZE; i++) {
    res.write(tmp_buf[i / SIZE][i % SIZE]);
  }
}

The Details pain in the report shows that transpose_and_fold.B4 is a pipelined loop with an II value of 6. The loop pipeline with this II value might affect the throughput of your design.

Figure 4. Function View of the transpose_and_fold Component

You can investigate further by checking the Loop Analysis report.

The Bottlenecks pane in the Loop Analysis Report shows that the II value is caused by a memory dependency on loads to the tmp_buf variable:
Figure 5. Loop Analysis Report Bottleneck and Details Panes for transpose_and_fold.B4


To see more information about the LSU in the System Viewer report, click on a node to display information about the LSU in the Details pane. In the figure below, the Details pane shows information like the latency and that the LSU is stall-free.

For stallable nodes, latency values provided are estimates.

Figure 6. Information in Details Pane for an LSU
When viewing a function, the Function View pane shows connections between nodes:
  • Control

    Control connections are connections between blocks and loops.

  • Memory

    Memory connections are connections between local memories, agent memories, or Avalon® MM Host interfaces.

  • Streams

    Stream connections are connections to and from read or write streams

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