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Ixiasoft
2.1.1. Constructing Communication Links in the Link Designer Module
2.1.2. Link and Simulation Setting
2.1.3. Transmitter Setting
2.1.4. Receiver Setting
2.1.5. IBIS-AMI Wrapper
2.1.6. Channel Setting
2.1.7. Batch Channel Simulation Configuration
2.1.8. Crosstalk Aggressor Transmitter Setting
2.1.9. Repeater and Retimer Configurations
2.1.10. Noise Source Link Component
2.1.11. System Options
2.1.12. Project Management Functions
2.1.13. Archiving and Unarchiving Projects
2.1.14. Device Model Importer
2.1.15. Analysis Functions and Pre-Simulation and Pre-Analysis Checklists
2.1.16. COM Analysis
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Ixiasoft
1. System Requirements and Installation Guide
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 22.3 |
Advanced Link Analyzer is a high-speed transceiver link simulator. When you design high-speed, multi-gigabit transceiver links, you must ensure the end-to-end performance from transmitter (TX) to receiver (RX) and all interconnects in between.
Advanced Link Analyzer's graphical user interface (GUI) and link simulator allows you to quickly and easily set up and evaluate high-speed link performance early in your design cycle. Advanced Link Analyzer also helps you identify possible issues in board level design. With Advanced Link Analyzer, you can quickly estimate optimal link equalization and other electrical parameter settings for transmitter and receiver. You can also use Advanced Link Analyzer to predict link performance such as jitter and noise at a small probability level.
Advanced Link Analyzer can simulate serial links with clock-forwarding structure. In this structure, a dedicated clock path is used to transmit a clock signal that the receiver uses for timing resolution tasks, such as equalization and data determination. To simulate clock-forwarding serial link, you need a clock signal IBIS-AMI transmitter and an IBIS-AMI receiver model that supports input clock signal. Currently, Advanced Link Analyzer supports clock-forwarding IBIS-AMI models as per Buffer Issue Resolution Documents (BIRD) 197, 204, 208, and 209 listed on the IBIS Open Forum.
Note: The clock path simulation support is a beta feature in the Intel® Quartus® Prime software version 22.3.