Visible to Intel only — GUID: mwh1410471014485
Ixiasoft
Visible to Intel only — GUID: mwh1410471014485
Ixiasoft
2.3. Intel® Quartus® Prime Tcl Packages
Package Name | Package Description |
---|---|
backannotate | Back-annotate the Compiler's assignments. |
bpps | Floorplan IP interfaces and other device resources in Interface Planner. |
chip_planner | Identify and modify resource usage and routing with the Chip Planner. |
design | Manipulate project databases, including the assignments database, to enable the creation of instance assignments without modifying the .qsf file. |
device | Get device and family information from the device database. |
dni_sdc | Set false path, input delay, or output delay SDC constraints. |
drc | Interact with Design Assistant design rule checks. |
eco | Specify engineering change orders after design compilation. |
external_memif_toolkit | Interact with external memory interfaces and debug components. |
fif | Contains the set of Tcl functions for using the Fault Injection File (FIF) Driver |
flng | Query properties of generic objects. |
flow | Compile a project, run command-line executables, and other compilation flows. |
help | Tcl command help. |
insystem_memory_edit | Read and edit memory contents in Intel FPGA devices. |
insystem_source_probe | Interact with the In-System Sources and Probes tool in an Intel device. |
interactive_synthesis | Interactive synthesis controls. |
ipgen | IP generation controls. |
iptclgen | Memory IP generation controls. |
jtag | Control the JTAG chain. |
logic_analyzer_interface | Query and modify the Logic Analyzer Interface output pin state. |
misc | Perform miscellaneous tasks such as enabling natural bus naming, package loading, and message posting. |
names | Gets or sets assignment names. |
periph | Interact with the interface pins. |
pfg | Controls the Programming File Generator. |
project | Create and manage projects and revisions, make any project assignments including timing assignments. |
project_ui | Query the GUI. |
qshm | Client and server controls. |
report | Get information from report tables, create custom reports. |
rtl | Traverse and query the RTL netlist of your design. |
sdc | Specify constraints and exceptions to the Timing Analyzer. |
sdc_ext | Intel FPGA-specific SDC commands. |
sta | Contains the set of Tcl functions for obtaining advanced information from the Timing Analyzer. |
stp | Run the Signal Tap Logic Analyzer. |
tdc | Obtain information from the Timing Analyzer. |
To keep memory requirements as low as possible, only the minimum number of packages load automatically with each Intel® Quartus® Prime executable. To run commands from other packages, load those packages beforehand.
Run your scripts with executables that include the packages you use in the scripts. For example, to use commands in the sdc_ext package, you must use the quartus_sta executable because quartus_sta is the only executable with support for the sdc_ext package.
The following command prints lists of the packages loaded or available to load for an executable, to the console:
<executable name> --tcl_eval help
For example, type the following command to list the packages loaded or available to load by the quartus_fit executable:
quartus_fit --tcl_eval help