Visible to Intel only — GUID: nik1410905452062
Ixiasoft
Visible to Intel only — GUID: nik1410905452062
Ixiasoft
5.1.7. Avalon-ST Descriptor Control Interface when Instantiated Separately
After fetching multiple descriptor entries from the Descriptor Table in the PCIe* system memory, the Descriptor Controller uses its Avalon® -ST Descriptor source interface to transfer 160-bit Descriptors to the Read or Write DMA Data Movers.
Signal Name |
Direction |
Description |
---|---|---|
RdAstRxData_i[159:0] |
Input |
Specifies the descriptors for the Read DMA module. Refer to DMA Descriptor Format table below for bit definitions. |
RdAstRxValid_i |
Input |
When asserted, indicates that the data is valid. |
RdAstRxReady_o |
Output |
When asserted, indicates that the Read DMA read module is ready to receive a new descriptor. The ready latency is 1 cycle. Consequently, interface can accept data 1 cycle after ready is asserted. |
Signal Name |
Direction |
Description |
---|---|---|
WrAstRxData_i[159:0] |
Input |
Specifies the descriptors for the Write DMA module. Refer to DMA Descriptor Format table below for bit definitions. |
WrAstRxValid_i |
Input |
When asserted, indicates that the data is valid. |
WrAstRxReady_o |
Output |
When asserted, indicates that the Write DMA module engine is ready to receive a new descriptor. The ready latency for this signal is 1 cycle. Consequently, interface can accept data 1 cycle after ready is asserted. |