Arria® 10 or Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* Solutions User Guide

ID 683425
Date 9/10/2024
Public
Document Table of Contents

5.1.7.2. Avalon® -ST Descriptor Status Sources

Read DMA and Write DMA modules report status to the Descriptor Controller on the RdDmaTxData_o[31:0] or WrDmaTxData_o[31:0] bus when a descriptor completes successfully.

The following table shows the mappings of the triggering events to the DMA descriptor status bus:

Table 41.  DMA Status Bus

Bits

Name

Description

[31:9]

Reserved

[8]

Done

When asserted, a single DMA descriptor has completed successfully.

[7:0] Descriptor ID The ID of the descriptor whose status is being reported.