Generic Serial Flash Interface Intel® FPGA IP User Guide

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ID 683419
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Generic Serial Flash Interface Intel® FPGA IP User Guide
1. Generic Serial Flash Interface Intel® FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Signals 1.4. Parameters 1.5. Register Map 1.6. Using Generic Serial Flash Interface Intel® FPGA IP 1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design 1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP 1.9. Intel HAL Driver 1.10. Generic Serial Flash Interface Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Generic Serial Flash Interface Intel® FPGA IP User Guide
1.6. Using Generic Serial Flash Interface Intel® FPGA IP x
1.6.1. Control Status Register Byte Enable 1.6.2. Memory Operations 1.6.3. Byte Enabling 1.6.4. Constraining the I/O Pins
1.6.3. Byte Enabling x
1.6.3.1. Byte Enabling Supported Patterns
1.6.4. Constraining the I/O Pins x
1.6.4.1. General Purpose I/O 1.6.4.2. Dedicated Active Serial Interface
1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design x
1.7.1. Hardware and Software Requirements 1.7.2. Functional Description 1.7.3. Creating Nios® II Hardware System 1.7.4. Integrating Modules into Quartus® Prime Project 1.7.5. Programming the .sof File 1.7.6. Building Application Software System using Nios® II Software Build Tools
1.7.2. Functional Description x
1.7.2.1. Reference Design Components 1.7.2.2. Reference Design Application Program
1.7.6. Building Application Software System using Nios® II Software Build Tools x
1.7.6.1. Reference Design Results
1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP x
1.8.1. Flash Operations that Require Operation Code 1.8.2. Flash Operations to Read Flash Registers 1.8.3. Flash Operations to Write Flash Registers 1.8.4. Flash Operations that Require An Address 1.8.5. Read Memory from the Flash 1.8.6. Program Flash
1.9. Intel HAL Driver x
1.9.1. Driver API
1. Generic Serial Flash Interface Intel® FPGA IP User Guide

1.3. Signals

Figure 1. Signal Block DiagramThe inclusion and width of some signals depend on the features selected.
Table 2.  Ports Description
Signal Width Direction Description
Avalon® Memory-Mapped Slave Interface for CSR (avl_csr) 5
avl_csr_addr 6 Input Avalon® memory-mapped address bus. The address bus is in word addressing.
avl_csr_read 1 Input Avalon® memory-mapped read control to the CSR.
avl_csr_rddata 32 Output Avalon® memory-mapped read data bus from the CSR.
avl_csr_write 1 Input Avalon® memory-mapped write control to the CSR.
avl_csr_wrdata 32 Input Avalon® memory-mapped write data bus to CSR.
avl_csr_waitrequest 1 Output Avalon® memory-mapped waitrequest control from the CSR.
avl_csr_rddata_valid 1 Output Avalon® memory-mapped read data valid that indicates the CSR read data is available.
avl_csr_byteenable 4 Input Avalon® memory-mapped byteenable control to the CSR. Available when you enable the Use byteenable for CSR parameter.
Avalon® Memory-Mapped Slave Interface for Memory Access (avl_mem) 5
avl_mem_write 1 Input Avalon® memory-mapped write control to the memory.
avl_mem_burstcount 7 Input Avalon® memory-mapped burst count for the memory. The value range from 1 to 64 (maximum page size).
avl_mem_waitrequest 1 Output Avalon® memory-mapped waitrequest control from the memory.
avl_mem_read 1 Input Avalon® memory-mapped read control to the memory.
avl_mem_addr N Input

Avalon® memory-mapped address bus. The address bus is in word addressing. The width of the address depends on the flash memory density.

If you are using Arria® 10, and Cyclone® 10 GX or any supported devices with general purpose I/O with multiples flashes, write the CSR to select the chip select. The IP targets the selected flash when being accessed via this address.
avl_mem_wrdata 32 Input Avalon® memory-mapped write data bus to the memory.
avl_mem_readddata 32 Output Avalon® memory-mapped read data bus from the memory.
avl_mem_rddata_valid 1 Output Avalon® memory-mapped read data valid that indicates the memory read data is available.
avl_mem_byteenble 4 Input Avalon® memory-mapped write data enable bus to memory. During the bursting mode, the byteenable bus is at logic high, 4’b1111.
Clock and Reset
clk 1 Input Input clock to clock the IP.
reset 1 Input Asynchronous reset to reset the IP.
Conduit Interface 6
qspi_pins_data 4 Bidirectional Input or output port to feed data from the flash device.
qspi_pins_dclk 1 Output Provides clock signal to the flash device.
qspi_pins_ncs 1/3 Output Provides the ncs signal to the flash device.
ASMI Block Interface 7
atom_ports_dclk 1 Output Clock signal from control-block based FPGA design to the external DCLK pin through the ASMI hard logic.
atom_ports_ncs 1/3 Output Chip select signal from control-block based FPGA design to the external nCSO pin through the ASMI hard logic.
atom_ports_oe 1 Output Active-low signal to enable DCLK and nCSO pins to reach the flash. The DCLK and nCSO are fixed to high when you set this signal to high, blocking the connection between control-block based FPGA and flash.
atom_ports_dataout 4 Output Control signal from control-block based FPGA design to the Active Serial data pin for sending data into the serial configuration device.
atom_ports_dataoe 4 Output Controls data pin either as input or output because the dedicated pins for active serial data is bidirectional.
atom_ports_datain 4 Input Signal from the Active Serial data pin to control-block based FPGA design.
5 You can only access one port (avl_csr or avl_mem) at a time. The IP allows subsequent access after it deasserts the waitrequest signals (avl_csr_waitrequest and avl_mem_waitrequest).
6 Available when you enable the Enable SPI pins interface parameter.
7 Available when you enable the Disable dedicated Active Serial interface parameter.
Level Two Title