Generic Serial Flash Interface Intel® FPGA IP User Guide

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ID 683419
Date 11/09/2021
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Document Table of Contents
Document Table of Contents x
1. Generic Serial Flash Interface Intel® FPGA IP User Guide
1. Generic Serial Flash Interface Intel® FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Signals 1.4. Parameters 1.5. Register Map 1.6. Using Generic Serial Flash Interface Intel® FPGA IP 1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design 1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP 1.9. Nios II HAL Driver 1.10. Generic Serial Flash Interface Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Generic Serial Flash Interface Intel® FPGA IP User Guide
1.6. Using Generic Serial Flash Interface Intel® FPGA IP x
1.6.1. Control Status Register Byte Enable 1.6.2. Memory Operations 1.6.3. Byte Enabling 1.6.4. Constraining the I/O Pins
1.6.3. Byte Enabling x
1.6.3.1. Byte Enabling Supported Patterns
1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design x
1.7.1. Hardware and Software Requirements 1.7.2. Functional Description 1.7.3. Creating Nios® II Hardware System 1.7.4. Integrating Modules into Intel® Quartus® Prime Project 1.7.5. Programming the .sof File 1.7.6. Building Application Software System using Nios® II Software Build Tools
1.7.2. Functional Description x
1.7.2.1. Reference Design Components 1.7.2.2. Reference Design Application Program
1.7.6. Building Application Software System using Nios® II Software Build Tools x
1.7.6.1. Reference Design Results
1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP x
1.8.1. Flash Operations that Require Operation Code 1.8.2. Flash Operations to Read Flash Registers 1.8.3. Flash Operations to Write Flash Registers Perform the Write Status Register Operation to Protect Sector of Flash 1.8.4. Flash Operations that Require An Address 1.8.5. Read Memory from the Flash 1.8.6. Program Flash
1.9. Nios II HAL Driver x
1.9.1. Driver API
1. Generic Serial Flash Interface Intel® FPGA IP User Guide

1.8.3. Flash Operations to Write Flash Registers

The following flash operations are used to write flash registers:

  • Write enhanced volatile configuration register
  • Write bank register
  • Write status register
  • Write configuration register
Note: You must execute the write enable operation before you start these operations.

The following registers are used to write the status of a register:

  • Flash command setting register
  • Flash command control register
  • Flash command write data 0 register

Perform the Write Status Register Operation to Protect Sector of Flash

proc write_status_register { } {
 global mp flash_cmd_setting flash_cmd_write_data_0 flash_cmd_ctrl
master_write_32 $mp $flash_cmd_setting 0x00001001
master_write_32 $mp $flash_cmd_write_data_0 0x0000007c
master_write_32 $mp $flash_cmd_ctrl 0x1
}

To perform the write status register operation, follow these steps:

  1. Define the global variables.
  2. Customize the write status register operation by writing to the flash command setting register.
    1. Set bit [7:0] of this register to 01 as 01h is the operation code of the write status register operation.
    2. Set bit [10:8] to 0 as this operation does not carry any address byte.
    3. Set bit 11 to 0 as the number of byte declared in bit [15:12] is the write data to the flash device.
    4. Set bit [15:12] to 1 as you will be writing 1 byte (8 bits) of data into the status register.
  3. Write the data to set the sector protection into the flash command write data 0 register.
    1. Bit 6 and bit [4:2] of the status register are the block protect bits and bit 5 is the Top/Bottom bit. In this example, protection is required for all sectors from the bottom of the memory array. For more information, refer to the respective flash datasheet.
  4. Write 1 to bit 0 of the flash command control register to start the write status register for the sector protect operation.
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