Visible to Intel only — GUID: wer1626365255155
Ixiasoft
1.1. CPRI Intel FPGA IP v19.7.0
1.2. CPRI Intel FPGA IP v19.6.1
1.3. CPRI Intel® FPGA IP v19.6.0
1.4. CPRI Intel® FPGA IP v19.5.0
1.5. CPRI Intel® FPGA IP v19.4.3
1.6. CPRI Intel® FPGA IP v19.4.2
1.7. CPRI Intel® FPGA IP v19.4.0
1.8. CPRI Intel® FPGA IP v19.3.0
1.9. CPRI Intel® FPGA IP v19.2.0
1.10. CPRI Intel® FPGA IP v18.1
1.11. CPRI v7.0 IP Core v17.1
1.12. CPRI v6.0 IP Core v17.0
1.13. CPRI v6.0 IP Core v14.1
1.14. CPRI v6.0 IP Core v14.0
1.15. CPRI v5.0 IP Core v13.1
1.16. CPRI v5.0 IP Core v13.0
Visible to Intel only — GUID: wer1626365255155
Ixiasoft
1.10. CPRI Intel® FPGA IP v18.1
Intel® Quartus® Prime Version | Description | Impact |
---|---|---|
18.1 | Changed the name of the IP to CPRI Intel® FPGA IP in Intel® Quartus® Prime IP Catalog. | — |
Renamed the IP parameter: Altera Debug Master Endpoint (ADME) to Native PHY Debug Master Endpoint (NPDME). | — | |
Added new register: IP_INFO. | — | |
Added new register bit in TX_SCR Register: tx_scr_active. | — | |
Added register DEBUG_STATUS at offset 0xA0 | ||
Added 12165.12 Mbps and 24330.24 Mbps line bit rate support for Intel® Stratix® 10 devices. | ||
Added the Hybrid core clocking mode. | ||
Added support for 64-bit interface. |