Visible to Intel only — GUID: bhc1410931829476
Ixiasoft
1. About This IP
2. Getting Started with Altera IPs
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Software Programming Interface
11. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives
12. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide
A. Ethernet Frame Format
B. Simulation Parameters
4.1.1. MAC Architecture
4.1.2. MAC Interfaces
4.1.3. MAC Transmit Datapath
4.1.4. MAC Receive Datapath
4.1.5. MAC Transmit and Receive Latencies
4.1.6. FIFO Buffer Thresholds
4.1.7. Congestion and Flow Control
4.1.8. Magic Packets
4.1.9. MAC Local Loopback
4.1.10. MAC Error Correction Code (ECC)
4.1.11. MAC Reset
4.1.12. PHY Management (MDIO)
4.1.13. Connecting MAC to External PHYs
4.2.1. 1000BASE-X/SGMII PCS Architecture
4.2.2. Transmit Operation
4.2.3. Receive Operation
4.2.4. Transmit and Receive Latencies
4.2.5. GMII Converter
4.2.6. SGMII Converter
4.2.7. Auto-Negotiation
4.2.8. Ten-bit Interface
4.2.9. PHY Loopback
4.2.10. PHY Power-Down
4.2.11. 1000BASE-X/SGMII PCS Reset
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17)
5.1.2. Statistics Counters (Dword Offset 0x18 – 0x38)
5.1.3. Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)
5.1.4. Supplementary Address (Dword Offset 0xC0 – 0xC7)
5.1.5. IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6)
5.1.6. Deterministic Latency (Dword Offset 0xE1– 0xE3)
5.1.7. IEEE 1588v2 Feature PMA Delay
6.1.1. 10/100/1000 Ethernet MAC Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.4. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (E-Tile)
6.1.5. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.7. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, SGMII Bridge, and Deterministic Latency Signals
6.1.8. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.9. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII TBI (LVDS I/O only) PCS Signals
6.1.10. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
6.1.11. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
6.1.12. 1000BASE-X/SGMII PCS Signals
6.1.13. 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.14. 1000BASE-X/SGMII PCS and PMA Signals
6.1.1.1. Clock and Reset Signals
6.1.1.2. Clock Enabler Signals
6.1.1.3. MAC Control Interface Signals
6.1.1.4. MAC Status Signals
6.1.1.5. MAC Receive Interface Signals
6.1.1.6. MAC Transmit Interface Signals
6.1.1.7. Pause and Magic Packet Signals
6.1.1.8. MII/GMII/RGMII Signals
6.1.1.9. PHY Management Signals
6.1.1.10. ECC Status Signals
6.1.11.1. IEEE 1588v2 RX Timestamp Signals
6.1.11.2. IEEE 1588v2 TX Timestamp Signals
6.1.11.3. IEEE 1588v2 TX Timestamp Request Signals
6.1.11.4. IEEE 1588v2 TX Insert Control Timestamp Signals
6.1.11.5. IEEE 1588v2 Time-of-Day (TOD) Clock Interface Signals
6.1.11.6. IEEE 1588v2 PCS Phase Measurement Clock Signal
6.1.11.7. IEEE 1588v2 PHY Path Delay Interface Signals
7.1. Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA
7.2. Sharing PLLs in Devices with LVDS Soft-CDR I/O
7.3. Sharing PLLs in Devices with GIGE PHY
7.4. Sharing Transceiver Quads
7.5. Migrating From Old to New User Interface For Existing Designs
7.6. Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA
10.6.1. alt_tse_mac_get_common_speed()
10.6.2. alt_tse_mac_set_common_speed()
10.6.3. alt_tse_phy_add_profile()
10.6.4. alt_tse_system_add_sys()
10.6.5. triple_speed_ethernet_init()
10.6.6. tse_mac_close()
10.6.7. tse_mac_raw_send()
10.6.8. tse_mac_setGMII mode()
10.6.9. tse_mac_setMIImode()
10.6.10. tse_mac_SwReset()
Visible to Intel only — GUID: bhc1410931829476
Ixiasoft
6.1.1.8. MII/GMII/RGMII Signals
Name | I/O | Description |
---|---|---|
GMII Transmit | ||
gm_tx_d[7:0] | I | GMII transmit data bus. |
gm_tx_en | O | Asserted to indicate that the data on the GMII transmit data bus is valid. |
gm_tx_err | O | Asserted to indicate to the PHY that the frame sent is invalid. |
GMII Receive | ||
gm_rx_d[7:0] | I | GMII receive data bus. |
gm_rx_dv | I | Assert this signal to indicate that the data on the GMII receive data bus is valid. Keep this signal asserted during frame reception, from the first preamble byte until the last byte of the CRC field is received. |
gm_rx_err | I | The PHY asserts this signal to indicate that the receive frame contains errors. |
RGMII Transmit | ||
rgmii_out[3:0] | O | RGMII transmit data bus. Drives gm_tx_d[3:0] on the positive edge of tx_clk and gm_tx_d[7:4] on the negative edge of tx_clk. |
tx_control | O | Control output signal. Drives gm_tx_en on the positive edge of tx_clk and a logical derivative of (gm_tx_en XOR gm_tx_err) on the negative edge of tx_clk. |
RGMII Receive | ||
rgmii_in[3:0] | I | RGMII receive data bus. Expects gm_rx_d[3:0] on the positive edge of rx_clk and gm_rx_d[7:4] on the negative edge of rx_clk. |
rx_control | I | RGMII control input signal. Expects gm_rx_dv on the positive edge of rx_clk and a logical derivative of (gm_rx_dv XOR gm_rx_err) on the negative edge of rx_clk. |
MII Transmit | ||
m_tx_d[3:0] | O | MII transmit data bus. |
m_tx_en | O | Asserted to indicate that the data on the MII transmit data bus is valid. |
m_tx_err | O | Asserted to indicate to the PHY device that the frame sent is invalid. |
MII Receive | ||
m_rx_d[3:0] | I | MII receive data bus. |
m_rx_en | I | Assert this signal to indicate that the data on the MII receive data bus is valid. Keep this signal asserted during frame reception, from the first preamble byte until the last byte of the CRC field is received. |
m_rx_err | I | The PHY asserts this signal to Indicate that the receive frame contains errors. |
MII PHY Status | ||
m_rx_col | I | Collision detection. The PHY asserts this signal to indicate a collision during frame transmission. This signal is not used in full- duplex or gigabit mode. |
m_rx_crs | I | Carrier sense detection. The PHY asserts this signal to indicate that it has detected transmit or receive activity on the Ethernet line. This signal is not used in full-duplex or gigabit mode. |