Visible to Intel only — GUID: bhc1410931446557
Ixiasoft
Visible to Intel only — GUID: bhc1410931446557
Ixiasoft
2.1.2. Generating a Design Example or Simulation Model
After you have parameterized the IP, you can also generate a design example, in addition to generating the IP component files.
In the IP parameter editor, click Example Design: "testbench" to create a functional simulation model (design example that includes a testbench). The testbench and the automated script are located in the <variation name>_testbench directory.
You can now integrate your custom IP instance in your design, simulate, and compile. While integrating your IP instance into your design, you must make appropriate pin assignments. You can create a virtual pin to avoid making specific pin assignments for top-level signals while you are simulating and not ready to map the design to hardware.
In the IP parameter editor, click Example Design: "example_design" to create the design example for the hardware test and simulation model for specific IP configurations on Stratix® 10 E-Tile devices. Refer to the Triple-Speed Ethernet Stratix® 10 FPGA IP Design Example User Guide for more details.