Visible to Intel only — GUID: bhc1410931388345
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1. About This IP
2. Getting Started with Altera IPs
3. Parameter Settings
4. Functional Description
5. Configuration Register Space
6. Interface Signals
7. Design Considerations
8. Timing Constraints
9. Testbench
10. Software Programming Interface
11. Triple-Speed Ethernet Intel® FPGA IP User Guide Archives
12. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP User Guide
A. Ethernet Frame Format
B. Simulation Parameters
4.1.1. MAC Architecture
4.1.2. MAC Interfaces
4.1.3. MAC Transmit Datapath
4.1.4. MAC Receive Datapath
4.1.5. MAC Transmit and Receive Latencies
4.1.6. FIFO Buffer Thresholds
4.1.7. Congestion and Flow Control
4.1.8. Magic Packets
4.1.9. MAC Local Loopback
4.1.10. MAC Error Correction Code (ECC)
4.1.11. MAC Reset
4.1.12. PHY Management (MDIO)
4.1.13. Connecting MAC to External PHYs
4.2.1. 1000BASE-X/SGMII PCS Architecture
4.2.2. Transmit Operation
4.2.3. Receive Operation
4.2.4. Transmit and Receive Latencies
4.2.5. GMII Converter
4.2.6. SGMII Converter
4.2.7. Auto-Negotiation
4.2.8. Ten-bit Interface
4.2.9. PHY Loopback
4.2.10. PHY Power-Down
4.2.11. 1000BASE-X/SGMII PCS Reset
5.1.1. Base Configuration Registers (Dword Offset 0x00 – 0x17)
5.1.2. Statistics Counters (Dword Offset 0x18 – 0x38)
5.1.3. Transmit and Receive Command Registers (Dword Offset 0x3A – 0x3B)
5.1.4. Supplementary Address (Dword Offset 0xC0 – 0xC7)
5.1.5. IEEE 1588v2 Feature (Dword Offset 0xD0 – 0xD6)
5.1.6. Deterministic Latency (Dword Offset 0xE1– 0xE3)
5.1.7. IEEE 1588v2 Feature PMA Delay
6.1.1. 10/100/1000 Ethernet MAC Signals
6.1.2. 10/100/1000 Multiport Ethernet MAC Signals
6.1.3. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.4. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and Embedded PMA Signals (E-Tile)
6.1.5. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.6. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.7. 10/100/1000 Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, SGMII Bridge, and Deterministic Latency Signals
6.1.8. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS Signals
6.1.9. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII TBI (LVDS I/O only) PCS Signals
6.1.10. 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
6.1.11. 10/100/1000 Multiport Ethernet MAC with 1000BASE-X/SGMII PCS and Embedded PMA Signals
6.1.12. 1000BASE-X/SGMII PCS Signals
6.1.13. 1000BASE-X/SGMII 2XTBI PCS Signals
6.1.14. 1000BASE-X/SGMII PCS and PMA Signals
6.1.1.1. Clock and Reset Signals
6.1.1.2. Clock Enabler Signals
6.1.1.3. MAC Control Interface Signals
6.1.1.4. MAC Status Signals
6.1.1.5. MAC Receive Interface Signals
6.1.1.6. MAC Transmit Interface Signals
6.1.1.7. Pause and Magic Packet Signals
6.1.1.8. MII/GMII/RGMII Signals
6.1.1.9. PHY Management Signals
6.1.1.10. ECC Status Signals
6.1.11.1. IEEE 1588v2 RX Timestamp Signals
6.1.11.2. IEEE 1588v2 TX Timestamp Signals
6.1.11.3. IEEE 1588v2 TX Timestamp Request Signals
6.1.11.4. IEEE 1588v2 TX Insert Control Timestamp Signals
6.1.11.5. IEEE 1588v2 Time-of-Day (TOD) Clock Interface Signals
6.1.11.6. IEEE 1588v2 PCS Phase Measurement Clock Signal
6.1.11.7. IEEE 1588v2 PHY Path Delay Interface Signals
7.1. Optimizing Clock Resources in Multiport MAC with PCS and Embedded PMA
7.2. Sharing PLLs in Devices with LVDS Soft-CDR I/O
7.3. Sharing PLLs in Devices with GIGE PHY
7.4. Sharing Transceiver Quads
7.5. Migrating From Old to New User Interface For Existing Designs
7.6. Clocking Scheme of MAC with 2XTBI PCS and Embedded PMA
10.6.1. alt_tse_mac_get_common_speed()
10.6.2. alt_tse_mac_set_common_speed()
10.6.3. alt_tse_phy_add_profile()
10.6.4. alt_tse_system_add_sys()
10.6.5. triple_speed_ethernet_init()
10.6.6. tse_mac_close()
10.6.7. tse_mac_raw_send()
10.6.8. tse_mac_setGMII mode()
10.6.9. tse_mac_setMIImode()
10.6.10. tse_mac_SwReset()
Visible to Intel only — GUID: bhc1410931388345
Ixiasoft
1.2. Device Family Support
The IP provides the following support for Altera device families.
Device Support Level | Definition |
---|---|
Advance | The IP is available for simulation and compilation for this device family. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (datapath width, burst depth, I/O standards tradeoffs). |
Preliminary | The IP is verified with preliminary timing models for this device family. The IP meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution. |
Final | The IP is verified with final timing models for this device family. The IP meets all functional and timing requirements for the device family and can be used in production designs. |
Device Family | Support | Minimum Speed Grade with 1588 Feature |
---|---|---|
Agilex™ 7 (E-Tile) | Final | Not supported |
Stratix® 10 (E-Tile) | Final | -I3 |
Stratix® 10 (L-Tile and H-Tile) | Final | -I3 |
Stratix® V | Final | -I3 |
Stratix® IV | Final | Not supported |
Arria® 10 | Final | -I3 |
Arria® V | Final | -I5 |
Arria® II | Final | Not supported |
Cyclone® 10 GX | Final | -I5 |
Cyclone® 10 LP | Final | Not supported |
Cyclone® V | Final | -I7 |
Cyclone® IV | Final | Not supported |
MAX® 10 | Final | -I7 |