Visible to Intel only — GUID: dsu1465589316173
Ixiasoft
5.1. Clock and Reset Interface Signals
Signal Name | Feature Support | Width (Bits) | I/O Direction | Description | ||||||||||||||||||||||||||||||||||||||||||||||||
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pll_ref_clk / pll_ref_clk[1:0] 11 | ILK and ILA | 1/2 | Input | Transceiver reference clock for the RX CDR PLL in IP core variations that target a Intel® Stratix® 10 device. The sets of valid frequencies vary with the per-lane data rate of the transceivers as following:
Note: pll_ref_clk[1] is only available when you enable Preserve unused transceiver channels for PAM4 parameter in E-tile PAM4 mode IP variations.
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tx_usr_clk | ILK only | 1 | Input | Transmit side user data interface clock. The lower frequency of tx_usr_clk increases the latency of data path. | ||||||||||||||||||||||||||||||||||||||||||||||||
rx_usr_clk | ILK only | 1 | Input | Receive side user data interface clock. The lower frequency of rx_usr_clk increases the latency of data path. | ||||||||||||||||||||||||||||||||||||||||||||||||
clk_tx_common | ILK and ILA | 1 | Output | Transmit PCS common lane clock driven by the SERDES transmit PLL.
The frequency is given by the following equation:
Frequency of clk_tx_common = transceiver data rate / PMA_WIDTHFor example, the clock rate is 322 MHz at 10.3125 Gbps transceiver speed with 32 bits.
The valid frequencies per lane data rate are as below:
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clk_rx_common | ILK and ILA | 1 | Output | Receive PCS common lane clock driven by CDR in transceiver.
The frequency is given by the following equation:
Frequency of clk_rx_common = transceiver data rate / PMA_WIDTHFor example, the clock rate is 322 MHz at 10.3125 Gbps transceiver speed with 32 bits PMA_WIDTH. The valid frequencies for clk_rx_common are same as clk_tx_common. |
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reset_n | ILK and ILA | 1 | Input | Active-low asynchronous reset signal. | ||||||||||||||||||||||||||||||||||||||||||||||||
tx_usr_srst | ILK and ILA | 1 | Output | Transmit-side reset output signal. Indicates the transmit side user data interface is resetting. This signal is synchronous with tx_usr_clk. | ||||||||||||||||||||||||||||||||||||||||||||||||
rx_usr_srst | ILK and ILA | 1 | Output | Receive-side reset output. Indicates the receive side user data interface is resetting. This signal is synchronous with rx_usr_clk. | ||||||||||||||||||||||||||||||||||||||||||||||||
mac_clkin | ILK and ILA | 1 | Input | This clock signal is only available in IP core variations that target an E-tile PAM4 device variations. This signal must be driven by a PLL and must use the same clock source that drives the pll_ref_clk. |
11 When you enable Preserve unused transceiver channels for PAM4 parameter, an additional reference clock port is added to preserve the unused PAM4 slave channel.
12 Only available in H-tile and L-tile device variations.
13 Only available in NRZ E-tile device variations.
14 Only available in PAM4 E-tile device variations.