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Ixiasoft
Visible to Intel only — GUID: nhq1560323081193
Ixiasoft
3.2.3. DCFIFO
The design uses two DCFIFO blocks at both TX and RX paths. The DCFIFO blocks handle data streaming and control signals for clock crossing between different clock domains.
Parameter | Value |
---|---|
lpm_width | (Number of lanes x 64)+32 |
lpm_numwords | 64 |
The format of the data that transmits through the FIFO is similar to the format generated by the traffic generator.
Control DCFIFO Data Out Bit | Signal | Description |
---|---|---|
[20] | tx_valid rx_valid |
Indicates TX or RX data is valid for Full and Basic modes. |
[19] | tx_start_of_packet rx_start_of_packet |
Indicates the start of a TX or RX data packet. For Full mode only. |
[18] | tx_end_of_packet rx_end_of_packet |
Indicates the end of a TX or RX data packet. For Full mode only. |
[17:10] | tx_channel rx_channel |
The channel number for data being transmitted or received on the current cycle number. For Full mode only. |
[9:5] | tx_empty rx_empty |
Indicates the number of non-valid words in the final burst of the TX or RX data. For Full mode only. |
[4:1] | tg_tx_num_valid_bytes_eob tc_rx_num_valid_bytes_eob |
Indicates the number of valid bytes in the last word of the final burst. For Full mode only. |
[0] | tg_tx_is_usr_cmd tc_rx_is_usr_cmd |
Initiates a user-defined information cycle.
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