AN 708: Application Note - PCI Express DMA Reference Design Using External Memory

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ID 683390
Date 5/17/2017
Public
Document Table of Contents
Document Table of Contents x
PCI Express DMA Reference Design Using External Memory
PCI Express DMA Reference Design Using External Memory x
Deliverables Included with the Reference Design Project Hierarchy Avalon-MM DMA Controller Reference Design DMA Operation Flow Running the Reference Design Understanding PCI Express Throughput Document Revision History
Project Hierarchy x
Parameter Settings for PCI Express Hard IP Variation Intel® Quartus® Prime Settings
Running the Reference Design x
Installing the Driver and Application Installing the Windows Software Installing the Hardware Running the Linux DMA Software Running the Windows DMA Software
Understanding PCI Express Throughput x
Throughput for Posted Writes Throughput for Reads
Throughput for Posted Writes x
Specifying the Maximum Payload Size
PCI Express DMA Reference Design Using External Memory

Parameter Settings for PCI Express Hard IP Variation

The Hard IP for PCI Express variant used in this reference design supports a 256-byte maximum payload size. The following tables list the values for all parameters.

Table 1.   System Settings

Parameter

Value

Number of lanes

Arria® V, Cyclone® V: x4

Intel® Arria® 10, Stratix® V: x8

Lane rate

Arria® V, Cyclone® V: Gen2 (5.0 Gbps)

Intel® Arria® 10, Stratix® V: Gen3 (8.0 Gbps)

RX buffer credit allocation – performance for received request

Low

Reference clock frequency

100 MHz

Enable configuration via the PCIe link

Disabled

Use ATX PLL

Disabled

Table 2.   Base Address Register (BAR) Settings

Parameter

Value

BAR0 Type

64-bit prefetchable memory

BAR0 Size

512 Bytes – 9 bits

BAR1

Disabled

BAR2 Type

Arria® V, Cyclone® V: 64-bit prefetchable memory

Intel® Arria® 10 Stratix® V: Disabled

BAR2 Size

Arria® V, Cyclone® V: 64 MByte (MB) – 26 bits

Intel® Arria® 10, Stratix® V: Disabled

BAR3

Disabled

BAR4 Type

Arria® V, Cyclone® V: Disabled

Intel® Arria® 10, Stratix® V: 64-bit prefetchable memory

BAR4 Size

Arria® V, Cyclone® V: Disabled

Intel® Arria® 10, Stratix® V: 256 MB – 28 bits

BAR5

Disabled

Table 3.  Device Identification Register Settings

Parameter

Value

Vendor ID

0x00001172

Device ID

0x0000E003

Revision ID

0x00000001

Class Code

Arria® V, Cyclone® V, Stratix® V: 0x00000000

Intel® Arria® 10: 0x00ff0000

Subsystem Vendor ID

Arria® V, Cyclone® V, Stratix® V: 0x00000000

Intel® Arria® 10: 0x00004e1b

Subsystem Device ID

Arria® V: 0x00000101

Cyclone® V: 0x00000000

Intel® Arria® 10: 0x00004e0c

Stratix® V: 0x0000b862

Table 4.   PCI Express/PCI Capabilities

Parameter

Value

Maximum payload size

Cyclone® V: 128 Bytes

Arria® V, Intel® Arria® 10, Stratix® V: 256 Bytes

Completion timeout range

ABCD

Implement Completion Timeout Disable

Enabled

Table 5.   Error Reporting Settings

Parameter

Value

Advanced error reporting (AER)

Disabled

ECRC checking

Disabled

ECRC generation

Disabled

Table 6.  Link Settings

Parameter

Value

Link port number

1

Slot clock configuration

Enabled

Table 7.  MSI and MSI-X Settings

Parameter

Value

Number of MSI messages requested

Arria® V, Intel® Arria® 10, Cyclone® V: 4

Stratix® V: 1

Implement MSI-X

Disabled

Table size

0

Table offset

0x0000000000000000

Table BAR indicator

0

Pending bit array (PBA) offset

0x0000000000000000

PBA BAR Indicator

0

Table 8.  Power Management

Parameter

Value

Endpoint L0s acceptable latency

Maximum of 64 ns

Endpoint L1 acceptable latency

Maximum of 1 us

Table 9.   PCIe Address Space Setting

Parameter

Value

Address width of accessible PCIe memory space

Arria® V, Cyclone® V: 32

Intel® Arria® 10: 40

Stratix® V: 64

Intel® Quartus® Prime Settings

The .qar file in the reference design package has the recommended synthesis, fitter, and timing analysis settings for the parameters specified in this reference design.

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