Parameter Settings for PCI Express Hard IP Variation
The Hard IP for PCI Express variant used in this reference design supports a 256-byte maximum payload size. The following tables list the values for all parameters.
Parameter |
Value |
---|---|
Number of lanes |
Arria® V, Cyclone® V: x4 Intel® Arria® 10, Stratix® V: x8 |
Lane rate |
Arria® V, Cyclone® V: Gen2 (5.0 Gbps) Intel® Arria® 10, Stratix® V: Gen3 (8.0 Gbps) |
RX buffer credit allocation – performance for received request |
Low |
Reference clock frequency |
100 MHz |
Enable configuration via the PCIe link |
Disabled |
Use ATX PLL |
Disabled |
Parameter |
Value |
---|---|
BAR0 Type |
64-bit prefetchable memory |
BAR0 Size |
512 Bytes – 9 bits |
BAR1 |
Disabled |
BAR2 Type |
Arria® V, Cyclone® V: 64-bit prefetchable memory Intel® Arria® 10 Stratix® V: Disabled |
BAR2 Size |
Arria® V, Cyclone® V: 64 MByte (MB) – 26 bits Intel® Arria® 10, Stratix® V: Disabled |
BAR3 |
Disabled |
BAR4 Type |
Arria® V, Cyclone® V: Disabled Intel® Arria® 10, Stratix® V: 64-bit prefetchable memory |
BAR4 Size |
Arria® V, Cyclone® V: Disabled Intel® Arria® 10, Stratix® V: 256 MB – 28 bits |
BAR5 |
Disabled |
Parameter |
Value |
---|---|
Vendor ID |
0x00001172 |
Device ID |
0x0000E003 |
Revision ID |
0x00000001 |
Class Code |
Arria® V, Cyclone® V, Stratix® V: 0x00000000 Intel® Arria® 10: 0x00ff0000 |
Subsystem Vendor ID |
Arria® V, Cyclone® V, Stratix® V: 0x00000000 Intel® Arria® 10: 0x00004e1b |
Subsystem Device ID |
Arria® V: 0x00000101 Cyclone® V: 0x00000000 Intel® Arria® 10: 0x00004e0c Stratix® V: 0x0000b862 |
Parameter |
Value |
---|---|
Maximum payload size |
Cyclone® V: 128 Bytes Arria® V, Intel® Arria® 10, Stratix® V: 256 Bytes |
Completion timeout range |
ABCD |
Implement Completion Timeout Disable |
Enabled |
Parameter |
Value |
---|---|
Advanced error reporting (AER) |
Disabled |
ECRC checking |
Disabled |
ECRC generation |
Disabled |
Parameter |
Value |
---|---|
Link port number |
1 |
Slot clock configuration |
Enabled |
Parameter |
Value |
---|---|
Number of MSI messages requested |
Arria® V, Intel® Arria® 10, Cyclone® V: 4 Stratix® V: 1 |
Implement MSI-X |
Disabled |
Table size |
0 |
Table offset |
0x0000000000000000 |
Table BAR indicator |
0 |
Pending bit array (PBA) offset |
0x0000000000000000 |
PBA BAR Indicator |
0 |
Parameter |
Value |
---|---|
Endpoint L0s acceptable latency |
Maximum of 64 ns |
Endpoint L1 acceptable latency |
Maximum of 1 us |
Parameter |
Value |
---|---|
Address width of accessible PCIe memory space |
Arria® V, Cyclone® V: 32 Intel® Arria® 10: 40 Stratix® V: 64 |
Intel® Quartus® Prime Settings
The .qar file in the reference design package has the recommended synthesis, fitter, and timing analysis settings for the parameters specified in this reference design.