AN 708: Application Note - PCI Express DMA Reference Design Using External Memory

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ID 683390
Date 5/17/2017
Public
Document Table of Contents
Document Table of Contents x
PCI Express DMA Reference Design Using External Memory
PCI Express DMA Reference Design Using External Memory x
Deliverables Included with the Reference Design Project Hierarchy Avalon-MM DMA Controller Reference Design DMA Operation Flow Running the Reference Design Understanding PCI Express Throughput Document Revision History
Project Hierarchy x
Parameter Settings for PCI Express Hard IP Variation
Running the Reference Design x
Installing the Driver and Application Installing the Windows Software Installing the Hardware Running the Linux DMA Software Running the Windows DMA Software
Understanding PCI Express Throughput x
Throughput for Posted Writes Throughput for Reads
Throughput for Posted Writes x
Specifying the Maximum Payload Size
PCI Express DMA Reference Design Using External Memory

DMA Operation Flow

Software completes the following steps to specify and initiate a DMA operation:

  1. Software allocates free memory space in the system memory to populate the descriptor table.
  2. Software allocates free space in the system memory for the data to be moved to and from the system memory by the DMA.
  3. Software writes all descriptors into the descriptor table in the system memory. The DMA supports up to 128 descriptors. Each descriptor has an ID, from descriptor ID 0 to descriptor ID 127. Each descriptor contains the source address, destination address, and size of the data to be moved. The source address specifies the location of the data to be moved from by the DMA. The destination address specifies the location that the data is moved to by the DMA.
  4. For the read DMA operation, the software initializes the system memory space with random data. The Read Data Mover moves this data from the system memory to the external memory. For the write DMA operation, the software initializes the external memory with random data. The Write Data Mover moves the data from the external memory to the system memory space.
  5. Software programs the registers in the Descriptor Controller's control logic through endpoint BAR0. Programming specifies the base address of the descriptor table which stores the descriptors in the system memory and the base address of the FIFO which is going to store the descriptors in the FPGA fabric domain. For this reference design, the base address is 0x80000000 for read DMA descriptor FIFO and 0x80002000 for write DMA descriptor FIFO.
  6. As the last step to start the DMA, software writes the ID of the last descriptor into the Descriptor Controller's control logic which triggers the Descriptor Controller to start the DMA. The DMA then starts fetching the descriptors from descriptor 0 to the last descriptor.
  7. After DMA fetches the last descriptor and transfers the data associated with that descriptor, the Descriptor Controller writes 1'b1 to the Done bit in the descriptor table header corresponding to the last descriptor in the PCIe domain through the Txs path.
  8. Software polls the Done bit in the descriptor table header corresponding to the last descriptor. The DMA operation completes when the Done bit is set and the performance is calculated. Once the DMA completes, the software compares the data in the system memory to the external memory. The test passes when there is no data mismatch.
  9. For simultaneous operation, the software begins the read DMA operation followed by the write DMA operation. The simultaneous operation is complete when both the read and write DMA operations finish.
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