The Nios II Gen2 processor family consists of /e and /f cores. It offers improvements over the Nios II Classic processor cores:

• Optional full 32-bit address space
• Optional user-defined Peripheral address region for data cache bypass
• Improved Qsys interface

The Nios II Gen2 /e core is completely backwards compatible with the Nios II Classic /s core. The Nios II Classic /s core has no direct equivalent in the Nios II Gen 2 family, however the Nios II Gen2 /f processor (as it has a more flexible configuration capability) can be configured to have the same feature set as the Nios II Classic /s core.

The Nios II Gen2 /f core offers the following feature enhancements over the Nios II Classic /f core:

• Optional full ECC support, including data cache and TCMs (Tightly-coupled Memories)
• Optional static branch prediction
• Higher performance multiplier
• Improved and more deterministic divider
• 64-bit multiply supported on all devices
• Improved low-cost shifter implementation up to 4 bits/cycle
• Instruction cache is now optional even when JTAG debug is present
• New system interface for system trace

For more detailed information on any of these features, refer to the Nios II Gen2 Processor Reference Guide.