1.3. Microcontroller I/O Expander Configuration
To set the port as input, output, or disabled, you must configure the I/O expander.
The I/O expander configuration data is a set of six bit registers:
- Four bits of I/O ports configuration (bits 5, 4, 3, and 2)
- Two bits of enabled port address (bits 1 and 0)
| Address | Bit | Function | Configuration |
|---|---|---|---|
| A7:A6 | 7–6 | No function | — |
| A5 | 5 | Configuration bit for Port D |
|
| A4 | 4 | Configuration bit for Port C |
|
| A3 | 3 | Configuration bit for Port B |
|
| A2 | 2 | Configuration bit for Port A |
|
| A1:A0 | 1–0 | Port address |
|
When the MODE signal is high and CS signal is low, the design places the configuration data on the input address bus (MCU port).
To activate the new configuration, send a single pulse of the CONF signal for one clock period. When the CONF signal and CS signals are low, the clock is enabled through the configuration registers. As a result, the I/O expander writes the configuration data in the configuration registers. This transition sets selected configuration as the state of the I/O expander.
If you want to select which of the four ports (A, B, C, or D) to use without configuring the ports, assert the LOAD signal low while CS signal is low. At the rising edge of the CLK signal, only the enabled port address data bits are written to the configuration registers.
The configuration of the selected port (input or output) also configures the MCU port direction. For example, if you configure port A as input and enable it, the direction of the MCU port becomes output. You cannot directly configure the input or output direction of the MCU port. However, if you need to access the configuration registers, use the MODE signal control pin to tri-state the MCU port and turn it into an input port.
The I/O expander design supports reset mode. When you assert the RST signal while the CS signal is low, all register contents are reset to zero asynchronously. All I/O expander including the MCU port are set to input mode, which is the initial state of the I/O expander.