F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 7/14/2022
Public

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2.1.1.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT)

The F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) with the parameters you specified. This component drives TLP data received to the PIO application. The DUT component is the F-Tile Avalon-ST IP for PCI Express Hard IP configured as Endpoint interacting with the root complex/switch at the other end. The DUT component translates the PCIe serial link transfer interface to Avalon-ST interface.