Unified FFT Intel FPGA IPs User Guide

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ID 683366
Date 4/05/2021
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Document Table of Contents
Document Table of Contents x
1. About the Unified FFT Intel FPGA IPs 2. Getting Started with the Unified FFT Intel FPGA IP 3. Bit-reverse Intel® FPGA IP 4. FFT Intel FPGA IP 5. Parallel FFT Intel FPGA IP 6. Variable Size Bit-reverse Intel FPGA IP 7. Variable Size FFT Intel FPGA IP 8. Unified FFT Intel FPGA IPs User Guide Archive 9. Document Revision History for the Unified FFT Intel FPGA IPs User Guide
1. About the Unified FFT Intel FPGA IPs x
1.1. Features of the Unified FFT Intel FPGA IPs 1.2. Unified FFT Intel FPGA IPs Device Family Support 1.3. Release Information for the Unified FFT IPs 1.4. Supported Data Types 1.5. FFT Spectrum 1.6. Global Enable
2. Getting Started with the Unified FFT Intel FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generating a Unified FFT IP 2.3. Compiling the Software Model for the Unified FFT IPs 2.4. Running the Unified FFT IPs Automatic Testbench
1. About the Unified FFT Intel FPGA IPs
2. Getting Started with the Unified FFT Intel FPGA IP
3. Bit-reverse Intel® FPGA IP
4. FFT Intel FPGA IP
5. Parallel FFT Intel FPGA IP
6. Variable Size Bit-reverse Intel FPGA IP
7. Variable Size FFT Intel FPGA IP
8. Unified FFT Intel FPGA IPs User Guide Archive
9. Document Revision History for the Unified FFT Intel FPGA IPs User Guide

2.3. Compiling the Software Model for the Unified FFT IPs

When you turn on Generate a software model, Intel Quartus Prime generates a software model of the IP in C++ language.

The software models are in the following directories depending on the IP:

  • intel_FPGA_unified_fft_10/sim/cmodel
  • intel_FPGA_unified_vfft_10/sim/cmodel
  • intel_FPGA_unified_pfft_10/sim/cmodel
  • intel_FPGA_unified_bitrev_10/sim/cmodel
  • intel_FPGA_unified_vbitrev_10/sim/cmodel

You need gcc 6.3.0 or MSVC++ 14.0 (Microsoft Visual Studio 2015) or later to compile the C++ model..

The cmodel directory contains the following files:

  • csl.h/cpp files containing utility functions and implementation details for the generated models.
  • instance_name.h or .cpp) files containing the simulation model of the IP and instance_name_atb.cpp containing the testbench of the IP.
  • atb_app.cpp file containing the main() function.
  • CMakeFiles.txt/CMakeLists.txt file containing CMake build scripts for building the ATB executable and model files.
  1. Generate the project or makefiles using CMakeLists.txt. For example, to generate Visual Studio 2017 projects, run:
    cmake -G "Visual Studio 15 2017 Win64"
    Or to generate a makefile for the release build with symbols on Linux:
    cmake -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=RelWithDebInfo
    Refer to the CMake documentation for more options.
  2. Set the MPIR_INC_PATH, MPIR_LIB_PATH, MPFR_INC_PATH, MPFR_LIB_PATH options to the include and library directories of builds of the mpfr or mpir libraries if the build scripts require them.
    You require the libraries if the internal bit widths in the software model are larger than 64-bits or when modeling certain floating-point configurations. The internal bit widths may be different to the bit widths that you choose. Build instructions and prebuilt binaries are on the mpfr or mpir websites.
  3. On Windows, open the generated solution file and run the compilation. On Linux, run make.
  4. Run the atb_app executable in the cmodel directory as the working directory so that the generated stimulus file paths are correct. If simulation is successful, the executable produces the following output to stdout: 
    Opening stimulus files... 
Simulating... 
Simulation has completed.
  5. Refer to the testbench to see how you can integrate the generated models into an existing system.
    The basic application programming interface (API) of the C++ model is: 
     // Create an instance of the C model class
unified_fft_c_model_t inst0;
 // Reset the model
 inst0.reset();
 // Note: this is a C Model of the RTL pipeline, so needs to be flushed to 
    get all the output just like RTL 
 while(there_is_input_or_expecting_output) { 
   // Write input
   inst0.write(io_chanIn_cunroll_x_t0);
   // Execute for all chanIn/Out structures
   inst0.execute(io_chanIn_cunroll_x_t0);
   // Execute for all chanIn/Out structures
   inst0.execute(io_chanOut_cunroll_x_t0);
   // Read output
   inst0.read(io_chanOut_cunroll_x_t0); 
 }
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