Visible to Intel only — GUID: mwh1409959064897
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Visible to Intel only — GUID: mwh1409959064897
Ixiasoft
2.5. Using Bridges
An Avalon® bridge has an Avalon® -MM slave interface and an Avalon® -MM master interface. You can have many components connected to the bridge slave interface, or many components connected to the bridge master interface. You can also have a single component connected to a single bridge slave or master interface.
You can configure the data width of the bridge, which can affect how Platform Designer generates bus sizing logic in the interconnect. Both interfaces support Avalon® -MM pipelined transfers with variable latency, and can also support configurable burst lengths.
Transfers to the bridge slave interface are propagated to the master interface, which connects to components downstream from the bridge. Bridges can provide more control over interconnect pipelining than the Limit interconnect pipeline stages to option.