Visible to Intel only — GUID: mwh1409958904872
Ixiasoft
Visible to Intel only — GUID: mwh1409958904872
Ixiasoft
3.2. Avalon® Streaming Interfaces
In this example, there are the following connection pairs:
- Data source in the Rx Interface transfers data to the data sink in the FIFO.
- Data source in the FIFO transfers data to the Tx Interface data sink.
The memory-mapped interface allows a processor to access the data source, FIFO, or data sink to provide system control. If your source and sink interfaces have different formats, for example, a 32-bit source and an 8-bit sink, Platform Designer automatically inserts the necessary adapters. You can view the adapters on the System View tab by clicking System > Show System with Platform Designer Interconnect.
The IP Catalog includes Avalon® -ST components that you can use to create datapaths, including datapaths whose input and output streams have different properties. Generated systems that include memory-mapped master and slave components may also use these Avalon® -ST components because Platform Designer generation creates interconnect with a structure similar to a network topology, as described in Platform Designer Transformations. The following sections introduce the Avalon® -ST components.