Visible to Intel only — GUID: mwh1409958831642
Ixiasoft
Visible to Intel only — GUID: mwh1409958831642
Ixiasoft
3.1. Memory-Mapped Interfaces
Platform Designer interconnect transmits memory-mapped transactions between masters and slaves in packets. The command network transports read and write packets from master interfaces to slave interfaces. The response network transports response packets from slave interfaces to master interfaces.
For each component interface, Platform Designer interconnect manages memory-mapped transfers and interacts with signals on the connected interface. Master and slave interfaces can implement different signals based on interface parameterizations, and Platform Designer interconnect provides any necessary adaptation between them. In the path between master and slaves, Platform Designer interconnect may introduce registers for timing synchronization, finite state machines for event sequencing, or nothing at all, depending on the services required by the interfaces.
Platform Designer interconnect supports the following implementation scenarios:
- Any number of components with master and slave interfaces. The master‑to‑slave relationship can be one‑to‑one, one‑to‑many, many‑to‑one, or many‑to‑many.
- Masters and slaves of different data widths.
- Masters and slaves operating in different clock domains.
- IP Components with different interface properties and signals. Platform Designer adapts the component interfaces so that interfaces with the following differences can be connected:
- Avalon® and AXI interfaces that use active‑high and active‑low signaling. AXI signals are active high, except for the reset signal.
- Interfaces with different burst characteristics.
- Interfaces with different latencies.
- Interfaces with different data widths.
- Interfaces with different optional interface signals.
Note: Since interface connections between AMBA* 3 AXI and AMBA* 4 AXI declare a fixed set of signals with variable latency, there is no need for adapting between active-low and active-high signaling, burst characteristics, different latencies, or port signatures. Adaptation might be necessary between Avalon® interfaces.
In this example, there are two components mastering the system, a processor and a DMA controller, each with two master interfaces. The masters connect through the Platform Designer interconnect to slaves in the Platform Designer system.
The dark blue blocks represent interconnect components. The dark gray boxes indicate items outside of the Platform Designer system and the Intel® Quartus® Prime software design, and show how to export component interfaces and how to connect these interfaces to external devices.
Section Content
Platform Designer Packet Format
Interconnect Domains
Master Network Interfaces
Slave Network Interfaces
Arbitration
Memory-Mapped Arbiter
Datapath Multiplexing Logic
Width Adaptation
Burst Adapter
Waitrequest Allowance Adapter
Read and Write Responses
Platform Designer Address Decoding