Visible to Intel only — GUID: mwh1409958976764
Ixiasoft
Visible to Intel only — GUID: mwh1409958976764
Ixiasoft
3.7. Interconnect Pipelining
Pipeline stages increase a design's fMAX by reducing the combinational logic depth, at the cost of additional latency and logic.
The Limit interconnect pipeline stages to option in the Interconnect Requirements tab allows you to define the maximum Avalon® -ST pipeline stages that Platform Designer can insert during generation. You can specify between 0 to 4 pipeline stages, where 0 means that the interconnect has a combinational datapath. Choosing 3 or 4 pipeline stages may significantly increase the logic utilization of the system.
Platform Designer adds additional latency once on the command path, and once on the response path.
This setting is specific for each Platform Designer system or subsystem, so you can specify a unique interconnect pipeline stage value for each subsystem.
The insertion of pipeline stages depends upon the existence of certain interconnect components. For example, single-slave systems do not have multiplexers; therefore, multiplexer pipelining does not occur. In an extreme case, of a single-master to single-slave system, no pipelining occurs, regardless of the value of the Limit interconnect pipeline stages to option.
You can manually adjust number of pipeline stages in the Platform Designer Memory-Mapped Interconnect tab.