Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

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ID 683364
Date 12/15/2018
Public
Document Table of Contents
Document Table of Contents x
1. Creating a System with Platform Designer 2. Optimizing Platform Designer System Performance 3. Platform Designer Interconnect 4. Platform Designer System Design Components 5. Creating Platform Designer Components 6. Platform Designer Command-Line Utilities 7. Component Interface Tcl Reference A. Intel® Quartus® Prime Standard Edition User Guides
1. Creating a System with Platform Designer x
1.1. Platform Designer Interface Support 1.2. Platform Designer System Design Flow 1.3. Starting or Opening a Project in Platform Designer 1.4. Viewing a Platform Designer System 1.5. Adding IP Components to a System 1.6. Connecting System Components 1.7. Specifying Interconnect Requirements 1.8. Defining Instance Parameters 1.9. Implementing Performance Monitoring 1.10. Configuring Platform Designer System Security 1.11. Upgrading Outdated IP Components 1.12. Synchronizing System Component Information 1.13. Generating a Platform Designer System 1.14. Simulating a Platform Designer System 1.15. Integrating a Platform Designer System with the Intel® Quartus® Prime Software 1.16. Managing Hierarchical Platform Designer Systems 1.17. Creating a System with Platform Designer Revision History
1.4. Viewing a Platform Designer System x
1.4.1. Viewing the System Hierarchy 1.4.2. Filtering the System View 1.4.3. Viewing Clock and Reset Domains 1.4.4. Viewing Avalon Memory-Mapped Domains in a System 1.4.5. Viewing the System Schematic 1.4.6. Viewing System Assignments and Connections 1.4.7. Customizing the Platform Designer Layout
1.4.3. Viewing Clock and Reset Domains x
1.4.3.1. Viewing Clock Domains in a System 1.4.3.2. Viewing Reset Domains in a System
1.5. Adding IP Components to a System x
1.5.1. Modifying IP Parameters 1.5.2. Applying Preset Parameters for Specific Applications 1.5.3. Adding Third-Party IP Components 1.5.4. Creating or Opening an IP Core Variant
1.5.1. Modifying IP Parameters x
1.5.1.1. Viewing Component or Parameter Details 1.5.1.2. Viewing a Component's Block Symbol
1.5.2. Applying Preset Parameters for Specific Applications x
1.5.2.1. Creating IP Custom Preset Parameters Settings
1.5.3. Adding Third-Party IP Components x
1.5.3.1. IP Search Path Recursive Search 1.5.3.2. Defining the IP Search Path with Index Files
1.5.3.1. IP Search Path Recursive Search x
1.5.3.1.1. IP Search Path Precedence 1.5.3.1.2. IP Component Description Files
1.6. Connecting System Components x
1.6.1. Platform Designer 64-Bit Addressing Support 1.6.2. Connecting Masters and Slaves 1.6.3. Changing a Conduit to a Reset 1.6.4. Wire-Level Connectivity 1.6.5. Previewing the System Interconnect
1.6.1. Platform Designer 64-Bit Addressing Support x
1.6.1.1. Support for Avalon® -MM Non-Power of Two Data Widths
1.6.4. Wire-Level Connectivity x
1.6.4.1. Editing Wire-Level Expressions 1.6.4.2. Wire-Level Expression Syntax 1.6.4.3. Adding or Removing Ports from Wire-Level Endpoint Interfaces 1.6.4.4. Scripting Wire-Level Expressions
1.7. Specifying Interconnect Requirements x
1.7.1. Interconnect Requirements
1.8. Defining Instance Parameters x
1.8.1. Creating an Instance Parameter Script in Platform Designer 1.8.2. Platform Designer Instance Parameter Script Tcl Commands
1.8.2. Platform Designer Instance Parameter Script Tcl Commands x
1.8.2.1. get_instance_parameter_value 1.8.2.2. get_instance_parameters 1.8.2.3. get_parameter_value 1.8.2.4. get_parameters 1.8.2.5. send_message 1.8.2.6. set_instance_parameter_value 1.8.2.7. set_module_property
1.10. Configuring Platform Designer System Security x
1.10.1. System Security Options 1.10.2. Specifying a Default Slave 1.10.3. Accessing Undefined Memory Regions
1.11. Upgrading Outdated IP Components x
1.11.1. Troubleshooting IP or Platform Designer System Upgrade
1.13. Generating a Platform Designer System x
1.13.1. Generation Dialog Box Options 1.13.2. Specifying the Generation ID 1.13.3. Files Generated for IP Cores and Platform Designer Systems 1.13.4. Generating System Testbench Files 1.13.5. Generating Example Designs for IP Components 1.13.6. Generating the HPS IP Component System View Description File 1.13.7. Generating Header Files for Master Components
1.13.4. Generating System Testbench Files x
1.13.4.1. Platform Designer Testbench Simulation Output Directories 1.13.4.2. Platform Designer Testbench Files
1.14. Simulating a Platform Designer System x
1.14.1. Adding Assertion Monitors for Simulation 1.14.2. Simulating Software Running on a Nios® II Processor
1.15. Integrating a Platform Designer System with the Intel® Quartus® Prime Software x
1.15.1. Integrate a Platform Designer System and the Intel® Quartus® Prime Software With the .qsys File 1.15.2. Integrate a Platform Designer System and the Intel® Quartus® Prime Software With the .qip File
1.16. Managing Hierarchical Platform Designer Systems x
1.16.1. Adding a Subsystem to a Platform Designer System 1.16.2. Viewing and Traversing Subsystem Contents 1.16.3. Editing a Subsystem 1.16.4. Changing a Component's Hierarchy Level 1.16.5. Saving a Subsystem 1.16.6. Exporting a System as an IP Component 1.16.7. Hierarchical System Using Instance Parameters Example
1.16.7. Hierarchical System Using Instance Parameters Example x
1.16.7.1. Create the Memory System 1.16.7.2. Add Platform Designer Instance Parameters 1.16.7.3. Create a Platform Designer Instantiating Memory System 1.16.7.4. Apply Instance Parameters at a Higher-Level Platform Designer System and Pass the Parameters to the Instantiated Lower-Level System
2. Optimizing Platform Designer System Performance x
2.1. Designing with Avalon® and AXI Interfaces 2.2. Using Hierarchy in Systems 2.3. Using Concurrency in Memory-Mapped Systems 2.4. Inserting Pipeline Stages to Increase System Frequency 2.5. Using Bridges 2.6. Increasing Transfer Throughput 2.7. Reducing Logic Utilization 2.8. Reducing Power Consumption 2.9. Reset Polarity and Synchronization in Platform Designer 2.10. Optimizing Platform Designer System Performance Design Examples 2.11. Optimizing Platform Designer System Performance Revision History
2.1. Designing with Avalon® and AXI Interfaces x
2.1.1. Designing Streaming Components 2.1.2. Designing Memory-Mapped Components
2.3. Using Concurrency in Memory-Mapped Systems x
2.3.1. Implementing Concurrency With Multiple Masters 2.3.2. Implementing Concurrency With Multiple Slaves 2.3.3. Implementing Concurrency with DMA Engines
2.5. Using Bridges x
2.5.1. Using Bridges to Increase System Frequency 2.5.2. Using Bridges to Minimize Design Logic 2.5.3. Using Bridges to Minimize Adapter Logic 2.5.4. Considering the Effects of Using Bridges
2.5.1. Using Bridges to Increase System Frequency x
2.5.1.1. Inserting Pipeline Bridges 2.5.1.2. Using Clock Crossing Bridges
2.5.1.1. Inserting Pipeline Bridges x
2.5.1.1.1. Implementing Command Pipelining (Master-to-Slave) 2.5.1.1.2. Implementing Response Pipelining (Slave-to-Master)
2.5.2. Using Bridges to Minimize Design Logic x
2.5.2.1. Avoiding Speed Optimizations That Increase Logic 2.5.2.2. Limiting Concurrency
2.5.3. Using Bridges to Minimize Adapter Logic x
2.5.3.1. Determining Effective Placement of Bridges 2.5.3.2. Changing the Response Buffer Depth
2.5.4. Considering the Effects of Using Bridges x
2.5.4.1. Increased Latency 2.5.4.2. Limited Concurrency 2.5.4.3. Address Space Translation 2.5.4.4. Address Coherency
2.5.4.1. Increased Latency x
2.5.4.1.1. Acceptable Latency Increase 2.5.4.1.2. Unacceptable Latency Increase
2.6. Increasing Transfer Throughput x
2.6.1. Using Pipelined Transfers 2.6.2. Arbitration Shares and Bursts
2.6.1. Using Pipelined Transfers x
2.6.1.1. Using the Maximum Pending Reads Parameter
2.6.2. Arbitration Shares and Bursts x
2.6.2.1. Differences Between Arbitration Shares and Bursts 2.6.2.2. Choosing Avalon® -MM Interface Types 2.6.2.3. Avalon® -MM Burst Master Example
2.6.2.2. Choosing Avalon® -MM Interface Types x
2.6.2.2.1. Simple Avalon® -MM Interfaces 2.6.2.2.2. Pipelined Avalon® -MM Interfaces 2.6.2.2.3. Burst Avalon® -MM Interfaces
2.7. Reducing Logic Utilization x
2.7.1. Minimizing Interconnect Logic to Reduce Logic Unitization 2.7.2. Minimizing Arbitration Logic by Consolidating Multiple Interfaces 2.7.3. Reducing Logic Utilization With Multiple Clock Domains 2.7.4. Duration of Transfers Crossing Clock Domains
2.7.1. Minimizing Interconnect Logic to Reduce Logic Unitization x
2.7.1.1. Creating Dedicated Master and Slave Connections to Minimize Interconnect Logic 2.7.1.2. Removing Unnecessary Connections to Minimize Interconnect Logic 2.7.1.3. Simplifying Address Decode Logic
2.7.2. Minimizing Arbitration Logic by Consolidating Multiple Interfaces x
2.7.2.1. Logic Consolidation Trade-Offs 2.7.2.2. Consolidating Interfaces
2.8. Reducing Power Consumption x
2.8.1. Reducing Power Consumption With Multiple Clock Domains 2.8.2. Reducing Power Consumption by Minimizing Toggle Rates 2.8.3. Reducing Power Consumption by Disabling Logic
2.10. Optimizing Platform Designer System Performance Design Examples x
2.10.1. Avalon Pipelined Read Master Example 2.10.2. Multiplexer Examples
2.10.1. Avalon Pipelined Read Master Example x
2.10.1.1. Avalon Pipelined Read Master Example Design Requirements 2.10.1.2. Expected Throughput Improvement
3. Platform Designer Interconnect x
3.1. Memory-Mapped Interfaces 3.2. Avalon® Streaming Interfaces 3.3. Interrupt Interfaces 3.4. Clock Interfaces 3.5. Reset Interfaces 3.6. Conduits 3.7. Interconnect Pipelining 3.8. Error Correction Coding (ECC) in Platform Designer Interconnect 3.9. AMBA* 3 AXI Protocol Specification Support (version 1.0) 3.10. AMBA* 3 APB Protocol Specification Support (version 1.0) 3.11. AMBA* 4 AXI Memory-Mapped Interface Support (version 2.0) 3.12. AMBA* 4 AXI Streaming Interface Support (version 1.0) 3.13. AMBA* 4 AXI-Lite Protocol Specification Support (version 2.0) 3.14. Port Roles (Interface Signal Types) 3.15. Platform Designer Interconnect Revision History
3.1. Memory-Mapped Interfaces x
3.1.1. Platform Designer Packet Format 3.1.2. Interconnect Domains 3.1.3. Master Network Interfaces 3.1.4. Slave Network Interfaces 3.1.5. Arbitration 3.1.6. Memory-Mapped Arbiter 3.1.7. Datapath Multiplexing Logic 3.1.8. Width Adaptation 3.1.9. Burst Adapter 3.1.10. Waitrequest Allowance Adapter 3.1.11. Read and Write Responses 3.1.12. Platform Designer Address Decoding
3.1.1. Platform Designer Packet Format x
3.1.1.1. Fields in the Platform Designer Packet Format 3.1.1.2. Transaction Types for Memory-Mapped Interfaces 3.1.1.3. Platform Designer Transformations
3.1.2. Interconnect Domains x
3.1.2.1. Using One Domain with Width Adaptation 3.1.2.2. Using Two Separate Domains
3.1.3. Master Network Interfaces x
3.1.3.1. Avalon® -MM Master Agent 3.1.3.2. Avalon® -MM Master Translator 3.1.3.3. AXI Master Agent 3.1.3.4. AXI Translator 3.1.3.5. APB Master Agent 3.1.3.6. APB Slave Agent 3.1.3.7. APB Translator 3.1.3.8. AHB Slave Agent 3.1.3.9. Memory-Mapped Router 3.1.3.10. Memory-Mapped Traffic Limiter
3.1.4. Slave Network Interfaces x
3.1.4.1. Avalon® -MM Slave Translator 3.1.4.2. AXI Translator 3.1.4.3. Wait State Insertion 3.1.4.4. Avalon® -MM Slave Agent 3.1.4.5. AXI Slave Agent
3.1.5. Arbitration x
3.1.5.1. Round-Robin Arbitration 3.1.5.2. Fixed Priority Arbitration
3.1.5.1. Round-Robin Arbitration x
3.1.5.1.1. Fairness-Based Shares 3.1.5.1.2. Round-Robin Scheduling
3.1.5.2. Fixed Priority Arbitration x
3.1.5.2.1. Designate a Platform Designer Slave to Use Fixed Priority Arbitration 3.1.5.2.2. Fixed Priority Arbitration with AXI Masters and Avalon® -MM Slaves
3.1.8. Width Adaptation x
3.1.8.1. Memory-Mapped Width Adapter
3.1.8.1. Memory-Mapped Width Adapter x
3.1.8.1.1. AXI Wide-to-Narrow Adaptation 3.1.8.1.2. AXI Narrow-to-Wide Adaptation
3.1.9. Burst Adapter x
3.1.9.1. Burst Adapter Implementation Options 3.1.9.2. Burst Adaptation: AXI to Avalon® 3.1.9.3. Burst Adaptation: Avalon® to AXI
3.2. Avalon® Streaming Interfaces x
3.2.1. Avalon® -ST Adapters
3.2.1. Avalon® -ST Adapters x
3.2.1.1. Avalon® -ST Adapter 3.2.1.2. Channel Adapter 3.2.1.3. Data Format Adapter 3.2.1.4. Error Adapter 3.2.1.5. Timing Adapter
3.2.1.1. Avalon® -ST Adapter x
3.2.1.1.1. Avalon® -ST Adapter Parameters Common to Source and Sink Interfaces 3.2.1.1.2. Avalon® -ST Adapter Upstream Source Interface Parameters 3.2.1.1.3. Avalon® -ST Adapter Downstream Sink Interface Parameters
3.2.1.2. Channel Adapter x
3.2.1.2.1. Avalon® -ST Channel Adapter Input Interface Parameters 3.2.1.2.2. Avalon® -ST Channel Adapter Output Interface Parameters 3.2.1.2.3. Avalon® -ST Channel Adapter Common to Input and Output Interface Parameters
3.2.1.3. Data Format Adapter x
3.2.1.3.1. Avalon® -ST Data Format Adapter Input Interface Parameters 3.2.1.3.2. Avalon® -ST Data Format Adapter Output Interface Parameters 3.2.1.3.3. Avalon® -ST Data Format Adapter Common to Input and Output Interface Parameters
3.2.1.4. Error Adapter x
3.2.1.4.1. Avalon® -ST Error Adapter Input Interface Parameters 3.2.1.4.2. Avalon® -ST Error Adapter Output Interface Parameters 3.2.1.4.3. Avalon® -ST Error Adapter Common to Input and Output Interface Parameters
3.2.1.5. Timing Adapter x
3.2.1.5.1. Avalon® -ST Timing Adapter Input Interface Parameters 3.2.1.5.2. Avalon® -ST Timing Adapter Output Interface Parameters 3.2.1.5.3. Avalon® -ST Timing Adapter Common to Input and Output Interface Parameters
3.3. Interrupt Interfaces x
3.3.1. Individual Requests IRQ Scheme 3.3.2. Assigning IRQs in Platform Designer
3.3.2. Assigning IRQs in Platform Designer x
3.3.2.1. IRQ Bridge 3.3.2.2. IRQ Mapper 3.3.2.3. IRQ Clock Crosser
3.4. Clock Interfaces x
3.4.1. (High Speed Serial Interface) HSSI Clock Interfaces
3.4.1. (High Speed Serial Interface) HSSI Clock Interfaces x
3.4.1.1. HSSI Serial Clock Interface 3.4.1.2. HSSI Bonded Clock Interface
3.4.1.1. HSSI Serial Clock Interface x
3.4.1.1.1. HSSI Serial Clock Source 3.4.1.1.2. HSSI Serial Clock Sink 3.4.1.1.3. HSSI Serial Clock Connection 3.4.1.1.4. HSSI Serial Clock Example
3.4.1.2. HSSI Bonded Clock Interface x
3.4.1.2.1. HSSI Bonded Clock Source 3.4.1.2.2. HSSI Bonded Clock Sink 3.4.1.2.3. HSSI Bonded Clock Connection 3.4.1.2.4. HSSI Bonded Clock Example
3.5. Reset Interfaces x
3.5.1. Single Global Reset Signal Implemented by Platform Designer 3.5.2. Reset Controller 3.5.3. Reset Bridge 3.5.4. Reset Sequencer
3.5.4. Reset Sequencer x
3.5.4.1. Reset Sequencer Parameters 3.5.4.2. Reset Sequencer Timing Diagrams 3.5.4.3. Reset Sequencer CSR Registers 3.5.4.4. Reset Sequencer Software Flows
3.5.4.3. Reset Sequencer CSR Registers x
3.5.4.3.1. Reset Sequencer Status Register 3.5.4.3.2. Reset Sequencer Interrupt Enable Register 3.5.4.3.3. Reset Sequencer Control Register 3.5.4.3.4. Reset Sequencer Software Sequenced Reset Assert Control Register 3.5.4.3.5. Reset Sequencer Software Sequenced Reset Deassert Control Register 3.5.4.3.6. Reset Sequencer Software Direct Controlled Resets 3.5.4.3.7. Reset Sequencer Software Reset Masking
3.5.4.4. Reset Sequencer Software Flows x
3.5.4.4.1. Reset Sequencer (Software-Triggered) Flow 3.5.4.4.2. Reset Assert Flow 3.5.4.4.3. Reset Deassert Flow 3.5.4.4.4. Reset Assert (Software Sequenced) Flow 3.5.4.4.5. Reset Deassert (Software Sequenced) Flow
3.7. Interconnect Pipelining x
3.7.1. Manually Control Pipelining in the Platform Designer Interconnect
3.9. AMBA* 3 AXI Protocol Specification Support (version 1.0) x
3.9.1. Channels 3.9.2. Cache Support 3.9.3. Security Support 3.9.4. Atomic Accesses 3.9.5. Response Signaling 3.9.6. Ordering Model 3.9.7. Data Buses 3.9.8. Unaligned Address Commands 3.9.9. Avalon® and AXI Transaction Support
3.9.1. Channels x
3.9.1.1. Read and Write Address Channels 3.9.1.2. Write Data, Write Response, and Read Data Channels 3.9.1.3. Low Power Channel
3.9.2. Cache Support x
3.9.2.1. Bufferable 3.9.2.2. Cacheable (Modifiable)
3.9.6. Ordering Model x
3.9.6.1. AXI and Avalon® Ordering
3.9.9. Avalon® and AXI Transaction Support x
3.9.9.1. Transaction Cannot Cross 4KB Boundaries 3.9.9.2. Handling Read Side Effects
3.10. AMBA* 3 APB Protocol Specification Support (version 1.0) x
3.10.1. Bridges 3.10.2. Burst Adaptation 3.10.3. Width Adaptation 3.10.4. Error Response
3.11. AMBA* 4 AXI Memory-Mapped Interface Support (version 2.0) x
3.11.1. Burst Support 3.11.2. QoS 3.11.3. Regions 3.11.4. Write Response Dependency 3.11.5. AWCACHE and ARCACHE 3.11.6. Width Adaptation and Data Packing in Platform Designer 3.11.7. Ordering Model 3.11.8. Read and Write Allocate 3.11.9. Locked Transactions 3.11.10. Memory Types 3.11.11. Mismatched Attributes 3.11.12. Signals
3.12. AMBA* 4 AXI Streaming Interface Support (version 1.0) x
3.12.1. Connection Points 3.12.2. Adaptation
3.12.1. Connection Points x
3.12.1.1. AMBA* 4 AXI Streaming Connection Point Parameters 3.12.1.2. AMBA* 4 AXI Streaming Connection Point Signals
3.13. AMBA* 4 AXI-Lite Protocol Specification Support (version 2.0) x
3.13.1. AMBA* 4 AXI-Lite Signals 3.13.2. AMBA* 4 AXI-Lite Bus Width 3.13.3. AMBA* 4 AXI-Lite Outstanding Transactions 3.13.4. AMBA* 4 AXI-Lite IDs 3.13.5. Connections Between AMBA* 3 AXI, AMBA* 4 AXI and AMBA* 4 AXI-Lite 3.13.6. AMBA* 4 AXI-Lite Response Merging
3.13.5. Connections Between AMBA* 3 AXI, AMBA* 4 AXI and AMBA* 4 AXI-Lite x
3.13.5.1. AMBA* 4 AXI-Lite Slave Requirements 3.13.5.2. AMBA* 4 AXI-Lite Data Packing
3.14. Port Roles (Interface Signal Types) x
3.14.1. AXI Master Interface Signal Types 3.14.2. AXI Slave Interface Signal Types 3.14.3. AMBA* 4 AXI Master Interface Signal Types 3.14.4. AMBA* 4 AXI Slave Interface Signal Types 3.14.5. AMBA* 4 AXI-Stream Master and Slave Interface Signal Types 3.14.6. ACE-Lite Interface Signal Roles 3.14.7. APB Interface Signal Types 3.14.8. Avalon® Memory-Mapped Interface Signal Roles 3.14.9. Avalon® Streaming Interface Signal Roles 3.14.10. Avalon® Clock Source Signal Roles 3.14.11. Avalon® Clock Sink Signal Roles 3.14.12. Avalon® Conduit Signal Roles 3.14.13. Avalon® Tristate Conduit Signal Roles 3.14.14. Avalon® Tri-State Slave Interface Signal Types 3.14.15. Avalon® Interrupt Sender Signal Roles 3.14.16. Avalon® Interrupt Receiver Signal Roles
4. Platform Designer System Design Components x
4.1. Bridges 4.2. Error Response Slave 4.3. Tri-State Components 4.4. Test Pattern Generator and Checker Cores 4.5. Avalon® -ST Splitter Core 4.6. Avalon® -ST Delay Core 4.7. Avalon® -ST Round Robin Scheduler 4.8. Avalon® Packets to Transactions Converter 4.9. Avalon® -ST Streaming Pipeline Stage 4.10. Streaming Channel Multiplexer and Demultiplexer Cores 4.11. Single-Clock and Dual-Clock FIFO Cores 4.12. Platform Designer System Design Components Revision History
4.1. Bridges x
4.1.1. Clock Bridge 4.1.2. Avalon® -MM Clock Crossing Bridge 4.1.3. Avalon® -MM Pipeline Bridge 4.1.4. Avalon® -MM Unaligned Burst Expansion Bridge 4.1.5. Bridges Between Avalon® and AXI Interfaces 4.1.6. AXI Bridge 4.1.7. AXI Timeout Bridge 4.1.8. Address Span Extender
4.1.2. Avalon® -MM Clock Crossing Bridge x
4.1.2.1. Avalon® -MM Clock Crossing Bridge Example 4.1.2.2. Avalon® -MM Clock Crossing Bridge Parameters
4.1.4. Avalon® -MM Unaligned Burst Expansion Bridge x
4.1.4.1. Using the Avalon® -MM Unaligned Burst Expansion Bridge 4.1.4.2. Avalon® -MM Unaligned Burst Expansion Bridge Parameters 4.1.4.3. Avalon® -MM Unaligned Burst Expansion Bridge Example
4.1.6. AXI Bridge x
4.1.6.1. AXI Bridge Signal Types 4.1.6.2. AXI Bridge Parameters 4.1.6.3. AXI Bridge Slave and Master Interface Parameters
4.1.7. AXI Timeout Bridge x
4.1.7.1. AXI Timeout Bridge Stages 4.1.7.2. AXI Timeout Bridge Parameters
4.1.8. Address Span Extender x
4.1.8.1. CTRL Register Layout 4.1.8.2. Address Span Extender Parameters 4.1.8.3. Calculating the Address Span Extender Slave Address 4.1.8.4. Using the Address Span Extender 4.1.8.5. Alternate Options for the Address Span Extender 4.1.8.6. Nios® II Support
4.2. Error Response Slave x
4.2.1. Error Response Slave Parameters 4.2.2. Error Response Slave CSR Registers 4.2.3. Designating a Default Slave
4.2.2. Error Response Slave CSR Registers x
4.2.2.1. Error Response Slave Access Violation Service 4.2.2.2. CSR Interrupt Status Registers 4.2.2.3. CSR Read Access Violation Log Registers 4.2.2.4. CSR Write Access Violation Log Registers
4.3. Tri-State Components x
4.3.1. Generic Tri-State Controller 4.3.2. Tri‑State Conduit Pin Sharer 4.3.3. Tri‑State Conduit Bridge
4.4. Test Pattern Generator and Checker Cores x
4.4.1. Test Pattern Generator 4.4.2. Test Pattern Checker 4.4.3. Software Programming Model for the Test Pattern Generator and Checker Cores 4.4.4. Test Pattern Generator API 4.4.5. Test Pattern Checker API
4.4.1. Test Pattern Generator x
4.4.1.1. Test Pattern Generator Command Interface 4.4.1.2. Test Pattern Generator Control and Status Interface 4.4.1.3. Test Pattern Generator Output Interface 4.4.1.4. Test Pattern Generator Functional Parameter
4.4.2. Test Pattern Checker x
4.4.2.1. Test Pattern Checker Input Interface 4.4.2.2. Test Pattern Checker Control and Status Interface 4.4.2.3. Test Pattern Checker Functional Parameter 4.4.2.4. Test Pattern Checker Input Parameters
4.4.3. Software Programming Model for the Test Pattern Generator and Checker Cores x
4.4.3.1. HAL System Library Support 4.4.3.2. Test Pattern Generator and Test Pattern Checker Core Files 4.4.3.3. Register Maps for the Test Pattern Generator and Test Pattern Checker Cores
4.4.3.3. Register Maps for the Test Pattern Generator and Test Pattern Checker Cores x
4.4.3.3.1. Test Pattern Generator Control and Status Registers 4.4.3.3.2. Test Pattern Generator Command Registers 4.4.3.3.3. Test Pattern Checker Control and Status Registers
4.4.4. Test Pattern Generator API x
4.4.4.1. data_source_reset() 4.4.4.2. data_source_init() 4.4.4.3. data_source_get_id() 4.4.4.4. data_source_get_supports_packets() 4.4.4.5. data_source_get_num_channels() 4.4.4.6. data_source_get_symbols_per_cycle() 4.4.4.7. data_source_get_enable() 4.4.4.8. data_source_set_enable() 4.4.4.9. data_source_get_throttle() 4.4.4.10. data_source_set_throttle() 4.4.4.11. data_source_is_busy() 4.4.4.12. data_source_fill_level() 4.4.4.13. data_source_send_data()
4.4.5. Test Pattern Checker API x
4.4.5.1. data_sink_reset() 4.4.5.2. data_sink_init() 4.4.5.3. data_sink_get_id() 4.4.5.4. data_sink_get_supports_packets() 4.4.5.5. data_sink_get_num_channels() 4.4.5.6. data_sink_get_symbols_per_cycle() 4.4.5.7. data_sink_get_enable() 4.4.5.8. data_sink_set enable() 4.4.5.9. data_sink_get_throttle() 4.4.5.10. data_sink_set_throttle() 4.4.5.11. data_sink_get_packet_count() 4.4.5.12. data_sink_get_error_count() 4.4.5.13. data_sink_get_symbol_count() 4.4.5.14. data_sink_get_exception() 4.4.5.15. data_sink_exception_is_exception() 4.4.5.16. data_sink_exception_has_data_error() 4.4.5.17. data_sink_exception_has_missing_sop() 4.4.5.18. data_sink_exception_has_missing_eop() 4.4.5.19. data_sink_exception_signalled_error() 4.4.5.20. data_sink_exception_channel()
4.5. Avalon® -ST Splitter Core x
4.5.1. Splitter Core Backpressure 4.5.2. Splitter Core Interfaces 4.5.3. Splitter Core Parameters
4.6. Avalon® -ST Delay Core x
4.6.1. Delay Core Reset Signal 4.6.2. Delay Core Interfaces 4.6.3. Delay Core Parameters
4.7. Avalon® -ST Round Robin Scheduler x
4.7.1. Almost-Full Status Interface (Round Robin Scheduler) 4.7.2. Request Interface (Round Robin Scheduler) 4.7.3. Round Robin Scheduler Operation 4.7.4. Round Robin Scheduler Parameters
4.8. Avalon® Packets to Transactions Converter x
4.8.1. Packets to Transactions Converter Interfaces 4.8.2. Packets to Transactions Converter Operation
4.8.2. Packets to Transactions Converter Operation x
4.8.2.1. Packets to Transactions Converter Data Packet Formats 4.8.2.2. Packets to Transactions Converter Supported Transactions 4.8.2.3. Packets to Transactions Converter Malformed Packets
4.10. Streaming Channel Multiplexer and Demultiplexer Cores x
4.10.1. Software Programming Model For the Multiplexer and Demultiplexer Components 4.10.2. Avalon® -ST Multiplexer 4.10.3. Avalon® -ST Demultiplexer
4.10.2. Avalon® -ST Multiplexer x
4.10.2.1. Multiplexer Input Interfaces 4.10.2.2. Multiplexer Output Interface 4.10.2.3. Multiplexer Parameters
4.10.3. Avalon® -ST Demultiplexer x
4.10.3.1. Demultiplexer Input Interface 4.10.3.2. Demultiplexer Output Interface 4.10.3.3. Demultiplexer Parameters
4.11. Single-Clock and Dual-Clock FIFO Cores x
4.11.1. Interfaces Implemented in FIFO Cores 4.11.2. FIFO Operating Modes 4.11.3. Fill Level of the FIFO Buffer 4.11.4. Almost-Full and Almost-Empty Thresholds to Prevent Overflow and Underflow 4.11.5. Single-Clock and Dual-Clock FIFO Core Parameters 4.11.6. Avalon® -ST Single-Clock FIFO Registers
4.11.1. Interfaces Implemented in FIFO Cores x
4.11.1.1. Avalon® -ST Data Interface 4.11.1.2. Avalon® -MM Control and Status Register Interface 4.11.1.3. Avalon® -ST Status Interface
5. Creating Platform Designer Components x
5.1. Platform Designer Components 5.2. Design Phases of an IP Component 5.3. Create IP Components in the Platform Designer Component Editor 5.4. Specify IP Component Type Information 5.5. Create an HDL File in the Platform Designer Component Editor 5.6. Create an HDL File Using a Template in the Platform Designer Component Editor 5.7. Specify Synthesis and Simulation Files in the Platform Designer Component Editor 5.8. Add Signals and Interfaces in the Platform Designer Component Editor 5.9. Specify Parameters in the Platform Designer Component Editor 5.10. Declaring SystemVerilog Interfaces in _hw.tcl 5.11. User Alterable HDL Parameters in _hw.tcl 5.12. Scripting Wire-Level Expressions 5.13. Control Interfaces Dynamically with an Elaboration Callback 5.14. Control File Generation Dynamically with Parameters and a Fileset Callback 5.15. Create a Composed Component or Subsystem 5.16. Create an IP Component with Platform Designer a System View Different from the Generated Synthesis Output Files 5.17. Add Component Instances to a Static or Generated Component 5.18. Creating Platform Designer Components Revision History
5.1. Platform Designer Components x
5.1.1. Platform Designer Interface Support 5.1.2. Component Structure 5.1.3. Component File Organization 5.1.4. Component Versions
5.1.4. Component Versions x
5.1.4.1. Upgrade IP Components to the Latest Version
5.3. Create IP Components in the Platform Designer Component Editor x
5.3.1. Save an IP Component and Create the _hw.tcl File 5.3.2. Edit an IP Component with the Platform Designer Component Editor
5.7. Specify Synthesis and Simulation Files in the Platform Designer Component Editor x
5.7.1. Specify HDL Files for Synthesis in the Platform Designer Component Editor 5.7.2. Analyze Synthesis Files in the Platform Designer Component Editor 5.7.3. Name HDL Signals for Automatic Interface and Type Recognition in the Platform Designer Component Editor 5.7.4. Specify Files for Simulation in the Component Editor 5.7.5. Include an Internal Register Map Description in the .svd for Slave Interfaces Connected to an HPS Component
5.9. Specify Parameters in the Platform Designer Component Editor x
5.9.1. Valid Ranges for Parameters in the _hw.tcl File 5.9.2. Types of Platform Designer Parameters 5.9.3. Declare Parameters with Custom _hw.tcl Commands 5.9.4. Validate Parameter Values with a Validation Callback
5.9.2. Types of Platform Designer Parameters x
5.9.2.1. Platform Designer User Parameters 5.9.2.2. Platform Designer System Information Parameters 5.9.2.3. Platform Designer Derived Parameters
5.9.2.3. Platform Designer Derived Parameters x
5.9.2.3.1. Parameterized Parameter Widths
5.17. Add Component Instances to a Static or Generated Component x
5.17.1. Static Components 5.17.2. Generated Components 5.17.3. Design Guidelines for Adding Component Instances
6. Platform Designer Command-Line Utilities x
6.1. Run the Platform Designer Editor with qsys-edit 6.2. Scripting IP Core Generation 6.3. Display Available IP Components with ip-catalog 6.4. Create an .ipx File with ip-make-ipx 6.5. Generate Simulation Scripts 6.6. Generate a Platform Designer System with qsys-script 6.7. Platform Designer Scripting Command Reference 6.8. Platform Designer Scripting Property Reference 6.9. Platform Designer Command-Line Interface Revision History
6.2. Scripting IP Core Generation x
6.2.1. qsys-generate Command-Line Options
6.7. Platform Designer Scripting Command Reference x
6.7.1. System 6.7.2. Subsystems 6.7.3. Instances 6.7.4. Connections 6.7.5. Top-level Exports 6.7.6. Validation 6.7.7. Miscellaneous 6.7.8. Wire-Level Connection Commands
6.7.1. System x
6.7.1.1. create_system 6.7.1.2. export_hw_tcl 6.7.1.3. get_device_families 6.7.1.4. get_devices 6.7.1.5. get_module_properties 6.7.1.6. get_module_property 6.7.1.7. get_project_properties 6.7.1.8. get_project_property 6.7.1.9. load_system 6.7.1.10. save_system 6.7.1.11. set_module_property 6.7.1.12. set_project_property
6.7.2. Subsystems x
6.7.2.1. get_composed_connections 6.7.2.2. get_composed_connection_parameter_value 6.7.2.3. get_composed_connection_parameters 6.7.2.4. get_composed_instance_assignment 6.7.2.5. get_composed_instance_assignments 6.7.2.6. get_composed_instance_parameter_value 6.7.2.7. get_composed_instance_parameters 6.7.2.8. get_composed_instances
6.7.3. Instances x
6.7.3.1. add_instance 6.7.3.2. apply_instance_preset 6.7.3.3. create_ip 6.7.3.4. add_component 6.7.3.5. duplicate_instance 6.7.3.6. enable_instance_parameter_update_callback 6.7.3.7. get_instance_assignment 6.7.3.8. get_instance_assignments 6.7.3.9. get_instance_documentation_links 6.7.3.10. get_instance_interface_assignment 6.7.3.11. get_instance_interface_assignments 6.7.3.12. get_instance_interface_parameter_property 6.7.3.13. get_instance_interface_parameter_value 6.7.3.14. get_instance_interface_parameters 6.7.3.15. get_instance_interface_port_property 6.7.3.16. get_instance_interface_ports 6.7.3.17. get_instance_interface_properties 6.7.3.18. get_instance_interface_property 6.7.3.19. get_instance_interfaces 6.7.3.20. get_instance_parameter_property 6.7.3.21. get_instance_parameter_value 6.7.3.22. get_instance_parameter_values 6.7.3.23. get_instance_parameters 6.7.3.24. get_instance_port_property 6.7.3.25. get_instance_properties 6.7.3.26. get_instance_property 6.7.3.27. get_instances 6.7.3.28. is_instance_parameter_update_callback_enabled 6.7.3.29. remove_instance 6.7.3.30. set_instance_parameter_value 6.7.3.31. set_instance_parameter_values 6.7.3.32. set_instance_property
6.7.4. Connections x
6.7.4.1. add_connection 6.7.4.2. auto_connect 6.7.4.3. get_connection_parameter_property 6.7.4.4. get_connection_parameter_value 6.7.4.5. get_connection_parameters 6.7.4.6. get_connection_properties 6.7.4.7. get_connection_property 6.7.4.8. get_connections 6.7.4.9. remove_connection 6.7.4.10. remove_dangling_connections 6.7.4.11. set_connection_parameter_value
6.7.5. Top-level Exports x
6.7.5.1. add_interface 6.7.5.2. get_exported_interface_sysinfo_parameter_value 6.7.5.3. get_exported_interface_sysinfo_parameters 6.7.5.4. get_interface_port_property 6.7.5.5. get_interface_ports 6.7.5.6. get_interface_properties 6.7.5.7. get_interface_property 6.7.5.8. get_interfaces 6.7.5.9. get_port_properties 6.7.5.10. remove_interface 6.7.5.11. set_interface_port_property 6.7.5.12. set_interface_property
6.7.6. Validation x
6.7.6.1. set_validation_property 6.7.6.2. validate_connection 6.7.6.3. validate_instance 6.7.6.4. validate_instance_interface 6.7.6.5. validate_system
6.7.7. Miscellaneous x
6.7.7.1. auto_assign_base_addresses 6.7.7.2. auto_assign_irqs 6.7.7.3. auto_assign_system_base_addresses 6.7.7.4. get_interconnect_requirement 6.7.7.5. get_interconnect_requirements 6.7.7.6. get_parameter_properties 6.7.7.7. lock_avalon_base_address 6.7.7.8. send_message 6.7.7.9. set_interconnect_requirement 6.7.7.10. set_use_testbench_naming_pattern 6.7.7.11. unlock_avalon_base_address 6.7.7.12. get_testbench_dutname 6.7.7.13. get_use_testbench_naming_pattern
6.7.8. Wire-Level Connection Commands x
6.7.8.1. set_wirelevel_expression 6.7.8.2. get_wirelevel_expressions 6.7.8.3. remove_wirelevel_expressions
6.8. Platform Designer Scripting Property Reference x
6.8.1. Connection Properties 6.8.2. Design Environment Type Properties 6.8.3. Direction Properties 6.8.4. Element Properties 6.8.5. Instance Properties 6.8.6. Interface Properties 6.8.7. Message Levels Properties 6.8.8. Module Properties 6.8.9. Parameter Properties 6.8.10. Parameter Status Properties 6.8.11. Parameter Type Properties 6.8.12. Port Properties 6.8.13. Project Properties 6.8.14. System Info Type Properties 6.8.15. Units Properties 6.8.16. Validation Properties 6.8.17. Interface Direction 6.8.18. File Set Kind 6.8.19. Access Type 6.8.20. Instantiation HDL File Properties 6.8.21. Instantiation Interface Duplicate Type 6.8.22. Instantiation Interface Properties 6.8.23. Instantiation Properties 6.8.24. Port Properties 6.8.25. VHDL Type
7. Component Interface Tcl Reference x
7.1. Platform Designer _hw.tcl Command Reference 7.2. Platform Designer _hw.tcl Property Reference 7.3. Component Interface Tcl Reference Revision History
7.1. Platform Designer _hw.tcl Command Reference x
7.1.1. Interfaces and Ports 7.1.2. Parameters 7.1.3. Display Items 7.1.4. Module Definition 7.1.5. Composition 7.1.6. Fileset Generation 7.1.7. Miscellaneous 7.1.8. SystemVerilog Interface Commands 7.1.9. Wire-Level Expression Commands
7.1.1. Interfaces and Ports x
7.1.1.1. add_interface 7.1.1.2. add_interface_port 7.1.1.3. get_interfaces 7.1.1.4. get_interface_assignment 7.1.1.5. get_interface_assignments 7.1.1.6. get_interface_ports 7.1.1.7. get_interface_properties 7.1.1.8. get_interface_property 7.1.1.9. get_port_properties 7.1.1.10. get_port_property 7.1.1.11. set_interface_assignment 7.1.1.12. set_interface_property 7.1.1.13. set_port_property 7.1.1.14. set_interface_upgrade_map
7.1.2. Parameters x
7.1.2.1. add_parameter 7.1.2.2. get_parameters 7.1.2.3. get_parameter_properties 7.1.2.4. get_parameter_property 7.1.2.5. get_parameter_value 7.1.2.6. get_string 7.1.2.7. load_strings 7.1.2.8. set_parameter_property 7.1.2.9. set_parameter_value 7.1.2.10. decode_address_map
7.1.3. Display Items x
7.1.3.1. add_display_item 7.1.3.2. get_display_items 7.1.3.3. get_display_item_properties 7.1.3.4. get_display_item_property 7.1.3.5. set_display_item_property
7.1.4. Module Definition x
7.1.4.1. add_documentation_link 7.1.4.2. get_module_assignment 7.1.4.3. get_module_assignments 7.1.4.4. get_module_ports 7.1.4.5. get_module_properties 7.1.4.6. get_module_property 7.1.4.7. send_message 7.1.4.8. set_module_assignment 7.1.4.9. set_module_property 7.1.4.10. add_hdl_instance 7.1.4.11. package
7.1.5. Composition x
7.1.5.1. add_instance 7.1.5.2. add_connection 7.1.5.3. get_connections 7.1.5.4. get_connection_parameters 7.1.5.5. get_connection_parameter_value 7.1.5.6. get_instances 7.1.5.7. get_instance_interfaces 7.1.5.8. get_instance_interface_ports 7.1.5.9. get_instance_interface_properties 7.1.5.10. get_instance_property 7.1.5.11. set_instance_property 7.1.5.12. get_instance_properties 7.1.5.13. get_instance_interface_property 7.1.5.14. get_instance_parameters 7.1.5.15. get_instance_parameter_property 7.1.5.16. get_instance_parameter_value 7.1.5.17. get_instance_port_property 7.1.5.18. set_connection_parameter_value 7.1.5.19. set_instance_parameter_value
7.1.6. Fileset Generation x
7.1.6.1. add_fileset 7.1.6.2. add_fileset_file 7.1.6.3. set_fileset_property 7.1.6.4. get_fileset_file_attribute 7.1.6.5. set_fileset_file_attribute 7.1.6.6. get_fileset_properties 7.1.6.7. get_fileset_property 7.1.6.8. get_fileset_sim_properties 7.1.6.9. set_fileset_sim_properties 7.1.6.10. create_temp_file
7.1.7. Miscellaneous x
7.1.7.1. check_device_family_equivalence 7.1.7.2. get_device_family_displayname 7.1.7.3. get_qip_strings 7.1.7.4. set_qip_strings 7.1.7.5. set_interconnect_requirement
7.1.8. SystemVerilog Interface Commands x
7.1.8.1. add_sv_interface 7.1.8.2. get_sv_interfaces 7.1.8.3. get_sv_interface_property 7.1.8.4. get_sv_interface_properties 7.1.8.5. set_sv_interface_property
7.1.9. Wire-Level Expression Commands x
7.1.9.1. set_wirelevel_expression 7.1.9.2. get_wirelevel_expressions 7.1.9.3. remove_wirelevel_expressions
7.2. Platform Designer _hw.tcl Property Reference x
7.2.1. Script Language Properties 7.2.2. Interface Properties 7.2.3. SystemVerilog Interface Properties 7.2.4. Instance Properties 7.2.5. Parameter Properties 7.2.6. Parameter Type Properties 7.2.7. Parameter Status Properties 7.2.8. Port Properties 7.2.9. Direction Properties 7.2.10. Display Item Properties 7.2.11. Display Item Kind Properties 7.2.12. Display Hint Properties 7.2.13. Module Properties 7.2.14. Fileset Properties 7.2.15. Fileset Kind Properties 7.2.16. Callback Properties 7.2.17. File Attribute Properties 7.2.18. File Kind Properties 7.2.19. File Source Properties 7.2.20. Simulator Properties 7.2.21. Port VHDL Type Properties 7.2.22. System Info Type Properties 7.2.23. Design Environment Type Properties 7.2.24. Units Properties 7.2.25. Operating System Properties 7.2.26. Quartus.ini Type Properties
1. Creating a System with Platform Designer
2. Optimizing Platform Designer System Performance
3. Platform Designer Interconnect
4. Platform Designer System Design Components
5. Creating Platform Designer Components
6. Platform Designer Command-Line Utilities
7. Component Interface Tcl Reference
A. Intel® Quartus® Prime Standard Edition User Guides

2.10.1.2. Expected Throughput Improvement

The throughput improvement that you can achieve with a pipelined read master is typically directly proportional to the pipeline depth of the interconnect and the slave interface. For example, if the total latency is two cycles, you can double the throughput by inserting a pipelined read master, assuming the slave interface also supports pipeline transfers. If either the master or slave does not support pipelined read transfers, then the interconnect asserts waitrequest until the transfer completes. You can also gain throughput when there are some cycles of overhead before a read response.

Where reads are not pipelined, the throughput is reduced. When both the master and slave interfaces support pipelined read transfers, data flows in a continuous stream after the initial latency. You can use a pipelined read master that stores data in a FIFO to implement a custom DMA, hardware accelerator, or off-chip communication interface.

Figure 75. Pipelined Read Master


This example shows a pipelined read master that stores data in a FIFO. The master performs word accesses that are word-aligned and reads from sequential memory addresses. The transfer length is a multiple of the word size.

When the go bit is asserted, the master registers the start_address and transfer_length signals. The master begins issuing reads continuously on the next clock cycle until the length register reaches zero. In this example, the word size is four bytes so that the address always increments by four, and the length decrements by four. The read signal remains asserted unless the FIFO fills to a predetermined level. The address register increments and the length register decrements if the length has not reached 0 and a read is posted.

The master posts a read transfer every time the read signal is asserted and the waitrequest is deasserted. The master issues reads until the entire buffer has been read or waitrequest is asserted. An optional tracking block monitors the done bit. When the length register reaches zero, some reads are outstanding. The tracking logic prevents assertion of done until the last read completes, and monitors the number of reads posted to the interconnect so that it does not exceed the space remaining in the readdata FIFO. This example includes a counter that verifies that the following conditions are met:

  • If a read is posted and readdatavalid is deasserted, the counter increments.
  • If a read is not posted and readdatavalid is asserted, the counter decrements.

When the length register and the tracking logic counter reach zero, all the reads have completed and the done bit is asserted. The done bit is important if a second master overwrites the memory locations that the pipelined read master accesses. This bit guarantees that the reads have completed before the original data is overwritten.

Level Two Title