JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683357
Date 10/21/2022
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Document Table of Contents
Document Table of Contents x
1. About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide 2. JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the JESD204C Design Example 4. JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the JESD204C Design Example x
3.1. System Components 3.2. JESD204C Design Example Clock and Reset 3.3. JESD204C Design Example Signals 3.4. JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. SYSREF Generator 3.1.5. Pattern Generator and Checker
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the JESD204C Design Example
4. JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

3.3. JESD204C Design Example Signals

Table 16.  System Interface Signals
Signal Direction Description
Clocks and Resets
mgmt_clk Input

100 MHz clock for system management.

refclk_xcvr Input

PLL/CDR reference clock for transceiver PHY.
refclk_core Input

Core PLL reference clock. Applies the same clock frequency as refclk_xcvr.

global_rst_n Input

Global reset signal from the push button. This reset is an active low signal and the deassertion of this signal is synchronous to the rising-edge of mgmt_clk.

in_sysref Input

SYSREF signal from external SYSREF generator for JESD204C Subclass 1 implementation.

sysref_out Output

SYSREF signal for JESD204C Subclass 1 implementation generated by the FPGA device for design example link initialization purpose only.

Signal Direction Description
SPI
spi_SS_n[2:0] Output

Active low, SPI slave select signal.

spi_SCLK Output

SPI serial clock.
spi_sdio
Note: When Generate 3-Wire SPI Module option is enabled.
Input/Output

Output data from the master to external slave. Input data from external slave to master.

spi_MISO
Note: When Generate 3-Wire SPI Module option is not enabled.
Input

Input data from external slave to the SPI master.

spi_MOSI
Note: When Generate 3-Wire SPI Module option is not enabled.
Output

Output data from SPI master to the external slave.

Signal Direction Description
ADC/DAC
tx_serial_data[LINK*L-1:0] Output

Differential high speed serial output data to DAC. The clock is embedded in the serial data stream.

tx_serial_data_n[LINK*L-1:0]
rx_serial_data[LINK*L-1:0] Input Differential high speed serial input data from ADC. The clock is recovered from the serial data stream.
rx_serial_data_n[LINK*L-1:0]
Signal Direction Description
General Purpose I/O
user_led[3:0] Output

Indicates the status for the following conditions:

  • [0]: SPI programming done
  • [1]: TX link error
  • [2]: RX link error
  • [3]: Pattern checker error for Avalon® streaming data
user_dip[3:0] Input

User mode DIP switch input:

  • [0]: Internal serial loopback enable
  • [1]: FPGA-generated SYSREF enable
  • [3:2]: Reserved

Signal

Direction

Description

Out-of-band (OOB) and Status
rx_patchk_data_error[LINK-1:0]

Output

When this signal is asserted, it indicates pattern checker has detected error.

rx_link_error[LINK-1:0]

Output

When this signal is asserted, it indicates JESD204C RX IP has asserted interrupt.

tx_link_error[LINK-1:0]

Output

When this signal is asserted, it indicates JESD204C TX IP has asserted interrupt.

emb_lock_out

Output

When this signal is asserted, it indicates JESD204C RX IP has achieved EMB lock.

sh_lock_out

Output

When this signal is asserted, it indicates JESD204C RX IP sync header is locked.

Signal

Direction

Description

Avalon Streaming
rx_avst_valid[LINK-1:0]

Input

Indicates whether the converter sample data to the application layer is valid or invalid.

  • 0: Data is invalid
  • 1: Data is valid
rx_avst_data[LINK-1:0][(TOTAL_SAMPLE*N)-1:0]

Input

Converter sample data to the application layer.
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