Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

Download PDF
ID 683354
Date 11/30/2020
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10GBASE-R Ethernet Design Example for Intel® Cyclone® 10 GX Devices 3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Cyclone® 10 GX Devices 4. Interface Signals Description 5. Configuration Registers Description 6. Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 7. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design 1.3. Compiling and Simulating the Design 1.4. Compiling and Testing the Design in Hardware
1.2. Generating the Design x
1.2.1. Procedure 1.2.2. Design Example Parameters
1.3. Compiling and Simulating the Design x
1.3.1. Procedure 1.3.2. Testbench
1.4. Compiling and Testing the Design in Hardware x
1.4.1. Procedure 1.4.2. Hardware Setup
2. 10GBASE-R Ethernet Design Example for Intel® Cyclone® 10 GX Devices x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Interface Signals 2.7. Configuration Registers
2.3. Functional Description x
2.3.1. Design Components 2.3.2. Clocking and Reset Scheme
2.5. Hardware Testing x
2.5.1. Test Cases
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Cyclone® 10 GX Devices x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Interface Signals 3.7. Configuration Registers
3.3. Functional Description x
3.3.1. Design Components 3.3.2. Clocking Scheme 3.3.3. Reset Scheme
3.4. Simulation x
3.4.1. Test Case
3.5. Hardware Testing x
3.5.1. Test Procedure
4. Interface Signals Description x
4.1. Clock and Reset Interface Signals 4.2. Avalon® Memory-Mapped Interface Signals 4.3. Avalon® Streaming Interface Signals 4.4. PHY Interface Signals 4.5. Status Interface
5. Configuration Registers Description x
5.1. Register Access Definition 5.2. Low Latency Ethernet 10G MAC 5.3. PHY
5.3. PHY x
5.3.1. 1G/2.5G/5G/10G Multi-rate PHY
1. Quick Start Guide
2. 10GBASE-R Ethernet Design Example for Intel® Cyclone® 10 GX Devices
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Cyclone® 10 GX Devices
4. Interface Signals Description
5. Configuration Registers Description
6. Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
7. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

4.2. Avalon® Memory-Mapped Interface Signals

Table 11.   Avalon® Memory-Mapped Interface Signals
Signal Direction Description

write

csr_mac_write

csr_phy_write

csr_mch_write

In Assert this signal to request a write.

read

csr_mac_read

csr_phy_read

csr_mch_read

In Assert this signal to request a read.

address

csr_mac_address

csr_phy_address

csr_mch_address 		In Use this bus to specify the register address you want to read from or write to.

writedata

csr_mac_writedata

csr_phy_writedata

csr_mch_writedata

In Carries the data to be written to the specified register.

readdata

csr_mac_readdata

csr_phy_readdata

csr_mch_readdata

Out Carries the data read from the specified register.

waitrequest

csr_mac_waitrequest

csr_phy_waitrequest

csr_mch_waitrequest

Out When asserted, this signal indicates that the IP is busy and not ready to accept any read or write requests.
Level Two Title