AN 742: PMBus SmartVID Controller Reference Designs

ID 683352
Date 5/08/2017
Public

1.1. Adapter Logic

The Adapter Logic module accepts the SmartVID outputs, stores them in a control and status register (CSR), and passes on the outputs to the Nios II processor through the Avalon-MM interface.
Figure 2. Adapter Logic Module
Table 1.  Configuration Register for Adapter Logic Module
Bit Register Offset Direction Reset Value Description
31:18 Reserved 0x4 RO All 0 Reserved.
17:8 temp_code 0x3 RO All 0 Temperature code—indicates the temperature code produced by the Temperature Sensor IP core.
7 vid_ack 0x2 WO 0 Receives a pulse from your controller when the vid_code signal is sampled and sent to the voltage regulator.
6:1 vid_code 0x1 RO Default Indicates the VID code produced by the SmartVID Controller IP core.
0 vid_code_avail 0x0 RO 0 Samples the VID code.