Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

Download PDF
ID 683349
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Intel® HLS Compiler Pro Edition Reference Manual 2. Compiler 3. C Language and Library Support 4. Component Interfaces 5. Component Memories (Memory Attributes) 6. Loops in Components 7. Component Concurrency 8. Arbitrary Precision Math Support 9. Component Target Frequency 10. Systems of Tasks 11. Libraries 12. Advanced Hardware Synthesis Controls 13. Intel® High Level Synthesis Compiler Pro Edition Reference Summary A. Advanced Math Source Code Libraries B. Supported Math Functions C. Cyclone® V Restrictions D. Intel® HLS Compiler Pro Edition Reference Manual Archives E. Document Revision History of the Intel® HLS Compiler Pro Edition Reference Manual
2. Compiler x
2.1. Intel® HLS Compiler Pro Edition Command Options 2.2. Using Libraries in Your Component 2.3. Compiler Interoperability 2.4. Intel® HLS Compiler Hardware Model
2.3. Compiler Interoperability x
2.3.1. Compiling Your Testbench and Component Separately
3. C Language and Library Support x
3.1. Supported C and C++ Subset for Component Synthesis 3.2. C and C++ Libraries 3.3. Templated and Overloaded Functions 3.4. Intel® HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros
3.3. Templated and Overloaded Functions x
3.3.1. Templated Functions 3.3.2. Overloaded Functions 3.3.3. Function Name Mapping
4. Component Interfaces x
4.1. Component Invocation Interface 4.2. Avalon® Streaming Interfaces 4.3. Pipes 4.4. Avalon® Memory-Mapped Host Interfaces 4.5. Agent Interfaces 4.6. Stable Component Parameters 4.7. Global Variables 4.8. Structs in Component Interfaces 4.9. Reset Behavior
4.1. Component Invocation Interface x
4.1.1. Scalar Parameters 4.1.2. Pointer and Reference Parameters 4.1.3. Interface Definition Example: Component Invocation Interface Control Attributes 4.1.4. Interface Definition Example: Component with Both Scalar and Pointer Arguments
4.3. Pipes x
4.3.1. The pipe Class and Its Use
4.4. Avalon® Memory-Mapped Host Interfaces x
4.4.1. Memory-Mapped Host Testbench Constructor 4.4.2. Implicit and Explicit Examples of Describing a Memory Interface 4.4.3. Avalon® Memory-Mapped Host Interfaces and Load-Store Units
4.4.3. Avalon® Memory-Mapped Host Interfaces and Load-Store Units x
4.4.3.1. Load-Store Unit Types 4.4.3.2. Memory-Access Coalescing and Load-Store Units
4.5. Agent Interfaces x
4.5.1. Control and Status Register (CSR) Agent 4.5.2. Agent Memories
5. Component Memories (Memory Attributes) x
5.1. Static Variables
6. Loops in Components x
6.1. Loop Initiation Interval (ii Pragma) 6.2. Loop-Carried Dependencies (ivdep Pragma) 6.3. Loop Coalescing (loop_coalesce Pragma) 6.4. Loop Unrolling (unroll Pragma) 6.5. Loop Concurrency (max_concurrency Pragma) 6.6. Loop Iteration Speculation (speculated_iterations Pragma) 6.7. Loop Pipelining Control (disable_loop_pipelining Pragma) 6.8. Loop Interleaving Control (max_interleaving Pragma) 6.9. Loop Fusion
6.9. Loop Fusion x
6.9.1. Loop Fusion Control (loop_fuse Pragma) 6.9.2. Loop Fusion Exemption (nofusion pragma)
7. Component Concurrency x
7.1. Serial Equivalence within a Memory Space or I/O 7.2. Concurrency Control (hls_max_concurrency Attribute) 7.3. Component Pipelining Control (hls_disable_component_pipelining Attribute)
8. Arbitrary Precision Math Support x
8.1. Declaring ac_int Data Types 8.2. Declaring ac_fixed Data Types 8.3. Declaring ac_complex Data Types 8.4. AC Data Types and Native Compilers 8.5. Declaring hls_float Data Types
8.1. Declaring ac_int Data Types x
8.1.1. Important Usage Information on the ac_int Data Type 8.1.2. Integer Promotion and ac_int Data Types 8.1.3. Debugging Your Use of the ac_int Data Type
8.2. Declaring ac_fixed Data Types x
8.2.1. Arbitrary Precision Fixed-Point Literals in Operations
8.5. Declaring hls_float Data Types x
8.5.1. Operators and Return Types Supported by the hls_float Data Type 8.5.2. Additional Data Types Provided By hls_float.h
9. Component Target Frequency x
9.1. Effects of Specifying Target II and Target fMAX
10. Systems of Tasks x
10.1. Task Functions 10.2. Internal Streams 10.3. System of Tasks Simulation
11. Libraries x
11.1. Static-Object Libraries 11.2. Creating a Static-Object Library 11.3. Creating Objects From HLS Code 11.4. Creating Objects From RTL Code 11.5. Packaging Object Files Into a Library
11.3. Creating Objects From HLS Code x
11.3.1. Creating an Object File From HLS Code 11.3.2. Supported OpenCL* Language Constructs
11.4. Creating Objects From RTL Code x
11.4.1. RTL Modules and the HLS Pipeline 11.4.2. Creating a Static-Object File from an RTL Module
11.4.1. RTL Modules and the HLS Pipeline x
11.4.1.1. Integration of an RTL Module into the HLS Pipeline 11.4.1.2. RTL Module Interfaces 11.4.1.3. RTL Reset and Clock Signals 11.4.1.4. Object Manifest File Syntax 11.4.1.5. Mapping HLS Data Types to RTL Signals 11.4.1.6. HLS Emulation Models for RTL-Based Functions 11.4.1.7. Potential Incompatibility between RTL Modules and Partial Reconfiguration 11.4.1.8. Stall-Free RTL 11.4.1.9. RTL Module Restrictions and Limitations for HLS Libraries
11.4.1.2. RTL Module Interfaces x
11.4.1.2.1. RTL Module Interface Signals
11.4.1.3. RTL Reset and Clock Signals x
11.4.1.3.1. Intel® Agilex™ and Intel® Stratix® 10 Design-Specific Reset Requirements for Stall-Free and Stallable RTL Modules
11.4.1.4. Object Manifest File Syntax x
11.4.1.4.1. XML Elements for ATTRIBUTES 11.4.1.4.2. XML Elements for INTERFACE 11.4.1.4.3. XML Elements for RESOURCES
11.4.1.4.1. XML Elements for ATTRIBUTES x
11.4.1.4.1.1. Interaction Between ALLOW_MERGINGand HAS_SIDE_EFFECTS Elements
12. Advanced Hardware Synthesis Controls x
12.1. Hardware Implementation Control for Math Functions 12.2. The hls_fpga_reg() Function
12.1. Hardware Implementation Control for Math Functions x
12.1.1. Math Function Hardware Implementation Summary 12.1.2. The --dsp-mode Command Option 12.1.3. The ihc::math_dsp_control Function
13. Intel® High Level Synthesis Compiler Pro Edition Reference Summary x
13.1. Intel® HLS Compiler Pro Edition i++ Command-Line Arguments 13.2. Intel® HLS Compiler Pro Edition Header Files 13.3. Intel® HLS Compiler Pro Edition Compiler-Defined Preprocessor Macros 13.4. Intel® HLS Compiler Pro Edition Keywords 13.5. Intel® HLS Compiler Pro Edition Simulation API (Testbench Only) 13.6. Intel® HLS Compiler Pro Edition Component Memory Attributes 13.7. Intel® HLS Compiler Pro Edition Loop Pragmas 13.8. Intel® HLS Compiler Pro Edition Scope Pragmas 13.9. Intel® HLS Compiler Pro Edition Component Attributes 13.10. Intel® HLS Compiler Pro Edition Component Default Interfaces 13.11. Intel® HLS Compiler Pro Edition Component Invocation Interface Control Attributes 13.12. Intel® HLS Compiler Pro Edition Component Macros 13.13. Intel® HLS Compiler Pro Edition Systems of Tasks API 13.14. Intel® HLS Compiler Pro Edition Pipes API 13.15. Intel® HLS Compiler Pro Edition Streaming Input Interfaces 13.16. Intel® HLS Compiler Pro Edition Streaming Output Interfaces 13.17. Intel® HLS Compiler Pro Edition Memory-Mapped Interfaces 13.18. Intel® HLS Compiler Pro Edition Load-Store Unit Control 13.19. Intel® HLS Compiler Pro Edition Arbitrary Precision Data Types
13.13. Intel® HLS Compiler Pro Edition Systems of Tasks API x
13.13.1. ihc::stream Class
A. Advanced Math Source Code Libraries x
A.1. Random Number Generator Library A.2. Matrix Multiplication Library A.3. Cholesky Decomposition Library
B. Supported Math Functions x
B.1. Math Functions Provided by the math.h Header File B.2. Math Functions Provided by the extendedmath.h Header File B.3. Math Functions Provided by the ac_fixed_math.h Header File B.4. Math Functions Provided by the hls_float.h Header File B.5. Math Functions Provided by the hls_float_math.h Header File B.6. Default Rounding Schemes and Subnormal Number Support
1. Intel® HLS Compiler Pro Edition Reference Manual
2. Compiler
3. C Language and Library Support
4. Component Interfaces
5. Component Memories (Memory Attributes)
6. Loops in Components
7. Component Concurrency
8. Arbitrary Precision Math Support
9. Component Target Frequency
10. Systems of Tasks
11. Libraries
12. Advanced Hardware Synthesis Controls
13. Intel® High Level Synthesis Compiler Pro Edition Reference Summary
A. Advanced Math Source Code Libraries
B. Supported Math Functions
C. Cyclone® V Restrictions
D. Intel® HLS Compiler Pro Edition Reference Manual Archives
E. Document Revision History of the Intel® HLS Compiler Pro Edition Reference Manual

13.6. Intel® HLS Compiler Pro Edition Component Memory Attributes

Use the component memory attributes to control the on-chip component memory architecture of your component.

Table 42.   Intel® HLS Compiler Pro Edition Component Memory Attributes Summary
Memory Attribute Description
hls_force_pow2_depth Specifies that the memory implementing the variable or array has power-of-2 depth.
hls_register Forces a variable or array to be carried through the pipeline in registers.

A register variable can be implemented either exclusively in flip-flops (FFs) or in a mix of FFs and RAM-based FIFOs.

hls_memory Forces a variable or array to be implemented as embedded memory.
hls_memory_impl Forces a variable or array to be implemented as embedded memory of a specified type.
hls_singlepump Specifies that the memory implementing the variable or array must be clocked at the same rate as the component accessing the memory.
hls_doublepump Specifies that the memory implementing the variable or array must be clocked at twice the rate as the component accessing the memory.
hls_numbanks Specifies that the memory implementing the variable or array must have a defined number of memory banks.
hls_bankwidth Specifies that the memory implementing the variable or array must have memory banks of a defined width.
hls_bankbits Forces the memory system to split into a defined number of memory banks and defines the bits used to select a memory bank.
hls_simple_dual_port_memory Specifies that the memory implementing the variable or array should have no port that services both reads and writes.
hls_merge (depthwise) Allows merging two or more local variables to be implemented in component memory as a single merged memory system in a depth-wise manner.
hls_merge (widthwise) Allows merging two or more local variables to be implemented in component memory as a single merged memory system in a width-wise manner.
hls_init_on_reset Forces the static variables inside the component to be initialized when the component reset signal is asserted.
hls_init_on_powerup Sets the component memory implementing the static variable to initialize on power-up when the FPGA is programmed.
hls_max_concurrency
Deprecated: This attribute is deprecated and will be removed in a future release. Use the hls_private_copies memory attribute instead.
Specifies that the memory implementing the variable or array has a defined number of private copies to allow concurrent iterations of a loop at any given time.
hls_max_replicates Specifies that the memory implementing the variable or array has no more than the specified number of replicates to enable simultaneous reads from the datapath
hls_private_copies Specifies that the memory implementing the variable or array has a defined number of private copies to allow concurrent iterations of a loop at any given time.

hls_force_pow2_depth Memory Attribute

Syntax
hls_force_pow2_depth(N)
Constraints
N can be only 0 or 1.
Default Value
1
Description
Specifies that the memory implementing the variable or array has a power-of-2 depth. This option is enabled if N is 1, and disabled if N is 0.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/component_memories/non_power_of_two_memory.

hls_register Memory Attribute

Syntax
hls_register
Constraints
N/A
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Forces a variable or array to be implemented as registers.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/swap_vs_copy.

hls_memory Memory Attribute

Syntax
hls_memory
Constraints
N/A
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Forces a variable or array to be implemented as embedded memory.

To learn more, review the following tutorial: <quartus_installdir>/hls/tutorials/component_memories/memory_implementation.

hls_memory_impl Memory Attribute

Syntax
hls_memory_impl("type")
Constraints
N/A
Default Value
Based on the memory size and memory access pattern inferred by the compiler.
Description

Forces a variable or array to be implemented as embedded memory of the specified type.

The type parameter can be one of the following values:
BLOCK_RAM
Implement the variable or array as memory blocks, such as M20K memory blocks.
MLAB
Implement the variable or array as memory logic array blocks (MLABs).

To learn more, review the following tutorial: <quartus_installdir>/hls/tutorials/component_memories/memory_implementation.

hls_singlepump Memory Attribute

Syntax
hls_singlepump
Constraints
N/A
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Specifies that the memory implementing the variable or array must be clocked at the same rate as the component accessing the memory.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/QRD.

hls_doublepump Memory Attribute

Syntax
hls_doublepump
Constraints
N/A
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Specifies that the memory implementing the variable or array must be clocked at twice the rate of the component accessing the memory.

To learn more, review the following tutorial: <quartus_installdir>/hls/tutorials/component_memories/memory_bank_configuration.

hls_numbanks Memory Attribute

Syntax
hls_numbanks(N)
Constraints
This attribute is subject to constraints outlined in Constraints on Attributes for Memory Banks.
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Specifies that the memory implementing the variable or array must have N banks, where N is a power-of-two constant number.

To learn more, review the following tutorial: <quartus_installdir>/hls/tutorials/component_memories/memory_geometry.

hls_bankwidth Memory Attribute

Syntax
hls_bankwidth(N)
Constraints
This attribute is subject to constraints outlined in Constraints on Attributes for Memory Banks.
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Specifies that the memory implementing the variable or array must have banks that are N bytes wide, where N is a power-of-two constant number.

To learn more, review the following tutorial: <quartus_installdir>/hls/tutorials/component_memories/memory_geometry.

hls_bankbits Memory Attribute

Syntax
hls_bankbits(b 0 , b 1 , ..., b n )
Constraints
This attribute is subject to constraints outlined in Constraints on Attributes for Memory Banks.
Default Value
Based on the memory access pattern inferred by the compiler.
Description
Forces the memory system to split into 2n+1 banks, with {b 0 , b 1 , ..., b n } forming the bank-select bits.
Important: b 0 , b 1 , ..., b n must be consecutive, positive integers. You can specify the consecutive, positive integers in ascending or descending order.

If you do not specify the hls_bankwidth(N) attribute along with this attribute, then b 0 , b 1 , ..., b n are mapped to array index bits 0 to n-1 in the memory bank implementation.

To learn more, review the following tutorial: <quartus_installdir>/hls/tutorials/component_memories/memory_geometry.

hls_simple_dual_port_memory Memory Attribute

Syntax
hls_simple_dual_port_memory
Constraints
N/A
Default Value
N/A
Description
Specifies that the memory implementing the variable or array should have no port that services both reads and writes.

To learn more, review the following tutorial: <quartus_installdir>/hls/tutorials/component_memories/memory_bank_configuration.

hls_merge (depthwise) Memory Attribute

Syntax
hls_merge("mem_name", "depth")
Constraints
N/A
Default Value
N/A
Description
Allows merging two or more local variables to be implemented in component memory as a single merged memory system in a depth-wise manner.

All variables with same <mem_name> label specified in their hls_merge attribute are merged into the same memory system.

To learn more, review the following tutorial: <quartus_installdir>/hls/tutorials/component_memories/memory_merging.

hls_merge (widthwise) Memory Attribute

Syntax
hls_merge("mem_name", "width")
Constraints
N/A
Default Value
N/A
Description
Allows merging two or more local variables to be implemented in component memory as a single merged memory system in a width-wise manner.

All variables with same <mem_name> label specified in their hls_merge attribute are merged into the same memory system.

To learn more, review the following tutorial: <quartus_installdir>/hls/tutorials/component_memories/memory_merging.

hls_init_on_reset Memory Attribute

Syntax
hls_init_on_reset
Constraints
N/A
Default Value
Default behavior for static variables.
Description
Forces the static variable inside the component to be initialized when the component reset signal is asserted. This requires an additional write port to the component memory implemented and can increase the power-up latency when the component is reset.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/component_memories/static_var_init.

hls_init_on_powerup Memory Attribute

Syntax
hls_init_on_powerup
Constraints
N/A
Default Value
N/A
Description
Sets the component memory implementing the static variable to initialize on power-up when the FPGA is programmed. When the component is reset, the component memory is not reset back to the initialized value of the static.

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/component_memories/static_var_init.

hls_max_concurrency Memory Attribute

Deprecated: This attribute is deprecated and will be removed in a future release. Use the hls_private_copies memory attribute instead.
Syntax
hls_max_concurrency(N)
Constraints
N/A
Default Value
N/A
Description
Specifies that the memory implementing the variable or array has N private copies to allow N concurrent iterations of a loop at any given time.

Apply this attribute only when the scope of a variable (through its declaration or access pattern) is limited to a loop. If the loop has the max_concurrency pragma applied to it, the number of private copies created is the lesser of the hls_max_concurrency memory attribute value and the max_concurrency pragma value.

hls_max_replicates Memory Attribute

Syntax
hls_max_replicates(N)
Constraints
N/A
Default Value
N/A
Description
Specifies that the memory implementing the variable or array has no more than the N replicates to enable simultaneous reads from the datapath.

To learn more, review the following tutorial: <quartus_installdir>/hls/tutorials/component_memories/memory_bank_configuration.

hls_private_copies Memory Attribute

Syntax
hls_private_copies(N)
Constraints
N/A
Default Value
N/A
Description
Specifies that the memory implementing the variable or array has N private copies to allow N concurrent iterations of a loop at any given time.

Apply this attribute only when the scope of a variable (through its declaration or access pattern) is limited to a loop. If the loop has the max_concurrency pragma applied to it, the number of private copies created is the lesser of the hls_private_copies memory attribute value and the max_concurrency pragma value.

Level Two Title