Chip ID Intel FPGA IP Cores User Guide

ID 683336
Date 9/26/2022
Public

Resetting the Chip ID Intel® Stratix® 10 FPGA IP Core

To reset the IP core, you must assert the reset signal for at least ten clock cycles.

Note:
  1. For Intel® Stratix® 10 devices, do not reset the IP core until at least tCD2UM after full chip initialization. Refer the respective device datasheet for tCD2UM value.
  2. For IP core instantiation guidelines, you must refer to the Intel® Stratix® 10 Reset Release IP section in the Intel® Stratix® 10 Configuration User Guide.