Chip ID Intel FPGA IP Cores User Guide

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ID 683336
Date 9/26/2022
Public
Document Table of Contents
Document Table of Contents x
Chip ID Intel® FPGA IP Cores User Guide
Chip ID Intel® FPGA IP Cores User Guide x
Device Support Chip ID Intel® Stratix® 10 FPGA IP Core Chip ID Intel® FPGA IP Cores Chip ID Intel® FPGA IP Cores User Guide Archives Document Revision History for the Chip ID Intel® FPGA IP Cores User Guide
Chip ID Intel® Stratix® 10 FPGA IP Core x
Functional Description Ports Accessing Chip ID Intel® Stratix® 10 FPGA IP through Signal Tap Resetting the Chip ID Intel® Stratix® 10 FPGA IP Core
Chip ID Intel® FPGA IP Cores x
Functional Description Ports Accessing Unique Chip ID Intel® Arria® 10 FPGA IP and Unique Chip ID Intel® Cyclone® 10 GX FPGA IP through Signal Tap Resetting the Chip ID Intel® FPGA IP Core
Chip ID Intel® FPGA IP Cores User Guide

Functional Description

The data_valid signal starts low in the initial state where no data is being read from the device. After feeding a clock signal to the clkin input port, the Chip ID Intel® FPGA IP core reads the unique chip ID. After reading, the IP core asserts the data_valid signal to indicate that the unique chip ID value at the output port is ready for retrieval. The operation repeats only when you reset the IP core.

The chip_id[63:0] output port holds the value of the unique chip ID until you reconfigure the device or reset the IP core.

Note: The Intel Chip ID IP core does not have simulation model files. To validate this IP core, Intel recommends that you perform hardware evaluation.
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