Ports
Port | I/O | Size (Bit) | Description |
---|---|---|---|
clkin | Input |
1 |
Feeds clock signal to the chip ID block. The maximum supported frequencies are as follows:
|
reset | Input |
1 |
Synchronous reset that resets the IP core. To reset the IP core, assert the reset signal high for at least 10 clkin cycles1. The chip_id [63:0]output port holds the value of the unique chip ID until you reconfigure the device or reset the IP core. |
data_valid | Output |
1 |
Indicates that the unique chip ID is ready for retrieval. If the signal is low, the IP core is in initial state or in progress to load data from a fuse ID. After the IP core asserts the signal, the data is ready for retrieval at the chip_id[63..0] output port. |
chip_id | Output |
64 |
Indicates the unique chip ID according to its respective fuse ID location. The data is only valid after the IP core asserts the data_valid signal. The value at power-up resets to 0. |