Chip ID Intel FPGA IP Cores User Guide

ID 683336
Date 9/26/2022
Public

Accessing Chip ID Intel® Stratix® 10 FPGA IP through Signal Tap

When you toggle the readid signal, the Chip ID Intel® Stratix® 10 FPGA IP core starts reading the chip ID from the Intel® Stratix® 10 device. When the chip ID is ready, the Chip ID Intel® Stratix® 10 FPGA IP core asserts the data_valid signal and ends the JTAG access.

Note: Allow a delay equivalent to tCD2UM after full chip configuration before attempting to read the unique chip ID. Refer the respective device datasheet for tCD2UM value.