Visible to Intel only — GUID: sss1456364911729
Ixiasoft
Accessing Unique Chip ID Intel® Arria® 10 FPGA IP and Unique Chip ID Intel® Cyclone® 10 GX FPGA IP through Signal Tap
Note: The Intel® Arria® 10 and Intel® Cyclone® 10 GX chip ID is inaccessible if you have other systems or IP cores accessing the JTAG simultaneously. For example, the Signal Tap II Logic Analyzer, Transceiver Toolkit, in-system signals or probes, and the SmartVID Controller IP core.
When you toggle the reset signal, the Unique Chip ID Intel® Arria® 10 FPGA IP and Unique Chip ID Intel® Cyclone® 10 GX FPGA IP cores start reading the chip ID from the Intel® Arria® 10 or Intel® Cyclone® 10 GX device. When the chip ID is ready, the Unique Chip ID Intel® Arria® 10 FPGA IP and Unique Chip ID Intel® Cyclone® 10 GX FPGA IP cores assert the data_valid signal and ends the JTAG access.
Note: Allow a delay equivalent to tCD2UM after full chip configuration before attempting to read the unique chip ID. Refer the respective device datasheet for tCD2UM value.