SDI Audio Intel® FPGA IP User Guide

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ID 683333
Date 6/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. SDI Audio Intel FPGA IP Overview 2. SDI Audio Intel FPGA IP Getting Started 3. SDI Audio Intel FPGA IP Functional Description 4. SDI Audio Intel FPGA IP Parameters 5. SDI Audio Intel FPGA IP Interface Signals 6. SDI Audio Intel FPGA IP Registers 7. SDI Audio Intel FPGA IP User Guide Archives 8. Document Revision History for the SDI Audio Intel FPGA IP User Guide
1. SDI Audio Intel FPGA IP Overview x
1.1. Release Information 1.2. Performance and Resource Utilization
2. SDI Audio Intel FPGA IP Getting Started x
2.1. Instantiating the SDI Audio Intel FPGA IP Simulating the Testbench
3. SDI Audio Intel FPGA IP Functional Description x
3.1. SDI Audio Embed IP Core 3.2. SDI Audio Extract IP Core 3.3. SDI Clocked Audio Input IP Core 3.4. SDI Clocked Audio Output IP Core 3.5. AES Format 3.6. Avalon Streaming Interface Audio Interface
4. SDI Audio Intel FPGA IP Parameters x
4.1. SDI Audio Embed IP Core Parameters 4.2. SDI Audio Extract IP Core Parameters 4.3. SDI Clocked Audio Input IP Core Parameters 4.4. SDI Clocked Audio Output IP Core Parameters
5. SDI Audio Intel FPGA IP Interface Signals x
5.1. SDI Audio Embed IP Core Signals 5.2. SDI Audio Extract IP Core Signals 5.3. SDI Audio Clocked Input Signals 5.4. SDI Audio Clocked Output Signals 5.5. SDI Audio IP Register Interface Signals
6. SDI Audio Intel FPGA IP Registers x
6.1. SDI Audio Embed Registers 6.2. SDI Audio Extract Registers 6.3. SDI Clocked Audio Input Registers 6.4. SDI Clocked Audio Output Registers
1. SDI Audio Intel FPGA IP Overview
2. SDI Audio Intel FPGA IP Getting Started
3. SDI Audio Intel FPGA IP Functional Description
4. SDI Audio Intel FPGA IP Parameters
5. SDI Audio Intel FPGA IP Interface Signals
6. SDI Audio Intel FPGA IP Registers
7. SDI Audio Intel FPGA IP User Guide Archives
8. Document Revision History for the SDI Audio Intel FPGA IP User Guide

3.6. Avalon Streaming Interface Audio Interface

To allow the standard components inside Platform Designer (Standard) to interconnect, you must define the Avalon streaming interface audio interface. The Avalon streaming interface audio interface must carry audio to and from physical AES3 interfaces, which means to support the AES3 outputs, the interface must transport the extra V, U, and C bits. You may create the P bit.

Each audio block consists of 192 frames, and each frame has channels 1 and 2. Each frame has a combination of the bits shown in the following figure.
Figure 5. AES Format

The Avalon streaming interface is a packet-based interface which carries audio information as a sequence of data packets. The functions define the types of packets as audio data packets and audio control packets.

Figure 6. Audio Data and Audio Control Packets for Avalon Streaming Interface Audio InterfaceThe sequence of audio control packets begins with V bit, U bit, and finally C bit. The audio control packets for U and C bits are similar to V bits.

The Avalon streaming interface audio protocol separates the audio data from the control or status data to facilitate audio data processing. The protocol defines that the data is packed LSB first, which matches the AES3 data. The audio data size is configurable at compile time and matches the audio data sample size. Including the aux, the audio data word is 24 bits.

In Avalon streaming interface audio, the data is packed as 24 bit symbols, typically with 1 symbol per beat [23:0]. The core transmits the audio control data as a packet after the audio data to meet the latency requirements.

The packet type identifier defines the packet type. The packet type identifier is the first value of any packet, when the start of packet signal is high. The audio data packet identifier is 0×A and the audio control data packet identifier is 0×E.

Table 4.  Avalon Streaming Interface Packet Types
Type Identifier Description
0 Video data packet
1–8 User packet types
10 Audio data packet
14 Audio control data packet
15 Video control data packet
9–15 Reserved

The preamble data, XYZ from AES, describes whether the data is at the start of a block and which channel the audio refers to. In Avalon streaming interface audio protocol, you are not required to transport the preamble data because the information stored in the data is described by the start of packet, end of packet, and channel signals.

The start of packet, end of packet, and channel signals indicate the start of the audio sample data and the associated audio channel.

For a single audio channel, the channel signal indicates channel 1 for all valid samples. The following figure shows an example of a single audio channel.

Figure 7. Single Audio Channel

For multiple channels, the Avalon streaming interface standard allows the packets to interleave across the channels. By interleaving, the interface allows multiple audio sources to be multiplexed and demultiplexed.

This figure shows an example of two audio channels, where the channel signal indicates either channel 1 or channel 2. Each channel has a start of packet and an end of packet signal, which allows interleaving and de-interleaving of the channel.

Figure 8. Multiple Audio Channels
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