SDI Audio Intel® FPGA IP User Guide

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ID 683333
Date 6/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. SDI Audio Intel FPGA IP Overview 2. SDI Audio Intel FPGA IP Getting Started 3. SDI Audio Intel FPGA IP Functional Description 4. SDI Audio Intel FPGA IP Parameters 5. SDI Audio Intel FPGA IP Interface Signals 6. SDI Audio Intel FPGA IP Registers 7. SDI Audio Intel FPGA IP User Guide Archives 8. Document Revision History for the SDI Audio Intel FPGA IP User Guide
1. SDI Audio Intel FPGA IP Overview x
1.1. Release Information 1.2. Performance and Resource Utilization
2. SDI Audio Intel FPGA IP Getting Started x
2.1. Instantiating the SDI Audio Intel FPGA IP Simulating the Testbench
3. SDI Audio Intel FPGA IP Functional Description x
3.1. SDI Audio Embed IP Core 3.2. SDI Audio Extract IP Core 3.3. SDI Clocked Audio Input IP Core 3.4. SDI Clocked Audio Output IP Core 3.5. AES Format 3.6. Avalon Streaming Interface Audio Interface
4. SDI Audio Intel FPGA IP Parameters x
4.1. SDI Audio Embed IP Core Parameters 4.2. SDI Audio Extract IP Core Parameters 4.3. SDI Clocked Audio Input IP Core Parameters 4.4. SDI Clocked Audio Output IP Core Parameters
5. SDI Audio Intel FPGA IP Interface Signals x
5.1. SDI Audio Embed IP Core Signals 5.2. SDI Audio Extract IP Core Signals 5.3. SDI Audio Clocked Input Signals 5.4. SDI Audio Clocked Output Signals 5.5. SDI Audio IP Register Interface Signals
6. SDI Audio Intel FPGA IP Registers x
6.1. SDI Audio Embed Registers 6.2. SDI Audio Extract Registers 6.3. SDI Clocked Audio Input Registers 6.4. SDI Clocked Audio Output Registers
1. SDI Audio Intel FPGA IP Overview
2. SDI Audio Intel FPGA IP Getting Started
3. SDI Audio Intel FPGA IP Functional Description
4. SDI Audio Intel FPGA IP Parameters
5. SDI Audio Intel FPGA IP Interface Signals
6. SDI Audio Intel FPGA IP Registers
7. SDI Audio Intel FPGA IP User Guide Archives
8. Document Revision History for the SDI Audio Intel FPGA IP User Guide

4.2. SDI Audio Extract IP Core Parameters

Table 6.  SDI Audio Extract IP Core Parameters
Parameter Value Description
Async Audio Interface On or Off

Turn on to enable the Asynchronous output.

This mode supports an audio clock equal to or higher than 64 × sample rate.
Parallel Audio Interface On or Off

Turn on to send AES data in parallel mode with a 32-bit parallel interface.

Requires Async Audio Interface to be turned on.

The actual audio sample rate is specified for serial data transmission. The equivalent audio sample rate in parallel mode matches the actual audio sample rate.

Include SD-SDI 24-bit support On or Off

Enables the extra logic to recover the EDP ancillary packets from SD-SDI inputs.
Channel status RAM On or Off

Turn on to store the received channel status data.
Include error checking On or Off

Turn on to enable extra error-checking logic to use the error status register.
Include status register On or Off

Turn on to enable extra logic to report the audio FIFO status on the fifo_status port or register.

Include clock On or Off

Turn on to enable the logic to recover both a sample rate clock and a 64 × sample rate clock.

With HD-SDI inputs, the core generates the output by using the embedded clock phase information.

With SD-SDI inputs, the core generates this output by using the counters running on the 27 MHz video clock. This generation limits the SD-SDI embedded audio to being synchronous to the video.

Include Avalon streaming interface On or Off

Turn on to include the SDI Clocked Audio Input IP core.

Turning on this parameter causes the Avalon streaming interface signals to appear at the top level. Otherwise, the audio input signals appear at the top level.

Include Avalon® memory-mapped interface control interface On or Off

Turn on to include the Avalon® memory-mapped interface control interface.

Turning on this parameter causes the register interface signals to appear at the top level. Otherwise, the direct control interface signals appear at the top level.

Related Information
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