Serial Lite III Streaming Intel® FPGA IP User Guide

ID 683330
Date 11/01/2021
Public

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5.4. Link-Up Sequence

Link-up Sequence for Intel® Stratix® 10 L-tile/H-tile Transceivers, Intel® Arria® 10, Stratix® V, and Arria® V Devices

For source core:
  1. The phy_mgmt_clk_reset signal de-asserts to indicate the Serial Lite III Streaming and Interlaken PHY IP or Native PHY IP cores are out of reset.
  2. Next, the tx_pll_locked signal asserts to indicate that all external transceiver PLLs are locked.
  3. The link_up_tx asserts to indicate that the Serial Lite III Streaming IP is ready to transmit data once the tx_ready signal from the Native PHY IP core for all lanes are asserted. During this time, the user_clock_reset_tx should be low.
For sink core:
  1. The phy_mgmt_clk_reset signal de-asserts to indicate the Serial Lite III Streaming and Interlaken PHY IP or Native PHY IP cores are out of reset.
  2. Next, the rx_ready signal from the Interlaken PHY IP or Native PHY IP cores, for all lanes asserts to indicate reset has complete for all RX lanes in the transceiver.
  3. Then, the link_up_rx signal is asserted to indicate that the Serial Lite III Streaming is ready to receive data from user interface. During this time, the user_clock_reset_rx should be low.
The sequence is illustrated in the following diagram.
Figure 10.  Serial Lite III Streaming IP Link Up Sequence

Link-up Sequence for Intel® Stratix® 10 E-tile Transceiver Devices

For source core:
  1. The phy_mgmt_clk_reset signal de-asserts to indicate the Serial Lite III Streaming and Native PHY IP core are out of reset.
  2. The link_up_tx asserts to indicate that the Serial Lite III Streaming IP is ready to transmit data once the tx_ready signal from the Native PHY IP core for all lanes are asserted. During this time, the user_clock_reset_tx should be low.
For sink core:
  1. The phy_mgmt_clk_reset signal de-asserts to indicate the Serial Lite III Streaming and Native PHY IP core are out of reset.
  2. Next, the rx_ready signal from the Interlaken PHY IP or Native PHY IP cores, for all lanes asserts to indicate reset has complete for all RX lanes in the transceiver.
  3. Then, the link_up_rx signal is asserted to indicate that the Serial Lite III Streaming is ready to receive data from user interface. During this time, the user_clock_reset_rx should be low.
The sequence is illustrated in the following diagram.